I've done the same thing as you but got different values:
-left border is 13 pixels so it should end with pixel 12, not 13
- HBLANK as we have defined it previously include the two borders (you didn't in your schema): it starts 320 pixels after the end of left border so it starts with pixel 333 (0xA6), not 0xA0. This is also probably where Vcounter is incremented (seems logical)
- Hint occurs 16 pixels before HBLANK start so it occurs at pixel 317 (0x9E)
Last point: with previous observations, we can tell VINT occurs at Hcount=0xF4 (which is the same as INT occurence in SMS mode)
There are still some errors with "H32 pixels" and MCLK during HBLANK
Check the other post for the exact repartition of "H32-like" and "H40-like" during HBLANK.
HSYNC is bounded by the front porch and the back porch:
right border > back porch -> HSYNC -> front porch -> left border
For V-INT interrupt, i calcul it happens juste before H-COUNTER = 0xFA.
I explain :
- According to Jorge Nuno Delay between H-INT and V-INT is 788 MCLKS.
- According to my schema, delay between H-INT and H-BLANK END is 988 MCLKS
- So V-INT happens 200 MCLKS before H-BLANK END
- 200/8 = 25 "H40 pixels"
- There are 13 pixels of left border so 25 - 13 = 12 pixels
- 419 -12 = 407
- So V-int occurs just after h-counter = 407 = 0xF9 -> just before H-Counter = 0xFA
224 Active display
8 Bottom border
3 Bottom blanking
3 Vertical blanking
13 Top blanking
11 Top border
V counter values
00-EA, E5-FF
If you look at the way he tested it, his "last line" you occurs 8 lines after the line where VINT occurs (line 224)
Well, we know bottom border is indeed 8 lines, so you can figure that the "first line" is in fact line 232 (starts of the bottom blanking)
If you take the rest: 3+3+13+11 = 30 lines
The first active line probably starts with Vcounter= 0 (VBLANK flag is set when VCOUNT=0xE0) but there is no way to know on which line the VDP really starts... this is not really important from an emulation point of view though.
Last edited by Eke on Mon Mar 09, 2009 5:32 pm, edited 3 times in total.
So the delay between H-INT and HBlankEnd is 990 MClks
The 68K needs 44 Clks (308 Mclks) to fetch registers before executing first instruction of the interrupt.
So the 68k can execute 682 MClks before the end of HBlank.
The problem is :
Before testing HBlank Flag in status register, there are others instructions at start at interrupt processus.
With my timings, the 68k can execute this instructions and test the hblank flag during this 682 MClks (before end of hblank) so the display is switch Off during this Hblank juste after the H-Int (line 107).
That's not normal because line 107 don't have to be displayed off !!!
I think that in real hardware, when the 68k do the first test of hblank flag, the first hblank period must be ended, so the display will be switched off next line.
Then maybe those timings are wrong or there is something more involved, who knows ?
This is the downside of speculating without doing any test, I told you
It would require someone willing to test exactly when the HBLANK flag is set/cleared regarding to the HINT occurence...
EDIt: I modified my schema
for example, something like this could fit as well (considering there was some latency while reading VDP status and HVcounter, we don't really know how this has been tested)
Have you the possibility eke to test this hblank flag timings (h-int + 406 -> hblank flag = 1, h-int + 988 -> hblank flag = 0) in genesis plus to see if you have the same problem with the first line of blue bar?
So with hblank cleared at H-int + 988 the game doesn't display correctly?
The only difference is that for me this is the first bar that is wrongly displayed.
