Cart Design Questions

Ask anything your want about Megadrive/Genesis programming.

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Chilly Willy
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Re: Cart Design Questions

Post by Chilly Willy » Sat May 18, 2019 2:31 pm

You should only drive /DTACK when the address is for your device. It should be tristated any other time. The MD drives the /DTACK line for other devices when the 68000 addresses them, like the VDP and work ram.

TmEE co.(TM)
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Re: Cart Design Questions

Post by TmEE co.(TM) » Sat May 18, 2019 7:37 pm

You can only drive !DTACK in 800000...9FFFFF range and other ranges (holes in IO ranges) where it isn't generated by VDP for you. In ranges where it is you will cause contention and that's gonna destroy something sooner or later.
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themrcul
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Re: Cart Design Questions

Post by themrcul » Sun May 19, 2019 5:15 am

Ok, so I will need to route the Ready/Busy line from the EEPROM through the CPLD to /DTACK, and tri-state the /DTACK line when in normal operation (ie when the PCB is being used in a Mega Drive) but when the CPLD knows it is being written to via the EEPROM writing device it can switch operation of the pin connected to /DTACK from tri-state to high and low, as it isn't connected to a Mega Drive but another device altogether.

It's a shame I can't save on two lines on the CPLD but it's better the device works than not! Thanks fellas.

Another quick question, I've noticed another line on the cartridge connector called /AS or address strobe. I'm having trouble finding literature on how it works - I've read that it takes 4 68k cycles to read data from ROM, and that it latches on the 3rd cycle. Does the /AS line get asserted at cycle 1 or 2 or something? Do you guys think it would be useful to have that line hooked up to the CPLD for timing purposes? I haven't seen any standard Mega Drive cartridge PCB hook the lines up for anything yet...

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Re: Cart Design Questions

Post by TmEE co.(TM) » Sun May 19, 2019 10:50 am

You can use !AS to latch the current address for decode purposes etc. I'm not sure if DMA uses it or not though.
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HardWareMan
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Re: Cart Design Questions

Post by HardWareMan » Sun May 19, 2019 5:05 pm

It is better to use !CAS2. When it asserts (goes to zero) there is sure stable address in any cycle, include DMA. The only problem with it is you've got shorter access time.

themrcul
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Re: Cart Design Questions

Post by themrcul » Mon May 27, 2019 2:59 am

Thanks guys. Interesting idea to use /CAS2 HardWareMan.

The EEPROM I am thinking of using (S29GL032N90TFI040) has a stated total access time of 110ns (this is for random access, not sequential page accesses) - do you think that 110ns is enough time for the EEPROM to be able to get the data if listening for /CAS2 to go low on the CPLD? Or would I be safer listening to /AS or /ASEL? The CPLD itself could be clocked up to 100MHz so the translation time from CPLD to EEPROM could be fast (10ns or so).

At first I was hoping that just listening on /CEO would be enough. I was planning on getting the CPLD to watch for a change on the /CEO line to 0, then it would also take the EEPROM output enable and read enable low to begin a read command. Likewise it would also be watching the /TIME line - when that line goes to 0 it would check the command attempting to be sent through using the /WRITE lines and the address and data lines and put that data into a buffer ready for the MCU to read it at another time.

But seeing that the /AS and /CAS2 lines exist seems to suggest that perhaps the data and address lines aren't always ready by the time /CEO or /TIME goes low - in which case I need to wait for both /CEO and /CAS2 or /TIME and /CAS2 - is that correct?
But do you think I should first wait for /CEO to go low, then also wait for /CAS2 to go low and then after that the CPLD can take both the EEPROM output enable and read enable lines low to perform a read? Or will just waiting for /CEO be enough?

Sadly I only have enough free lines on the CPLD to route four of the following signals:
/CEO
/CAS0
/CAS2
/AS
/ASEL
/WRITE LOW
/WRITE HIGH

I could theoretically drop write high, as all accesses through will be word reads and writes. Any byte write access will be on odd address lines as well. That would mean I could hook up /CEO, /CAS2, /AS and /WRITE LOW.

So, do you guys know if 130ns is too slow to wait from the assertion of /CAS2 to there needing to be data on the data lines? 130 nano seconds is calculated from 110ns of EEPROM, 5ns of translation time of SN74LVTH16245A x 2, and 10ns of CPLD clock translation. I have read that 150ns is the speed required for DMA to work without glitches, sounds like I'd be cutting it closely...

Thanks again for your help.

themrcul
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Re: Cart Design Questions

Post by themrcul » Mon May 27, 2019 7:00 am

Ok, so from what you guys have written at the end of this thread: Gen Cart Pinout viewtopic.php?f=13&t=517&start=15 /AS is not asserted for DMA, so for my purposes it is useless.
So I may as well connect:
/CEO
/CAS0
/CAS2
/WRL

This should give me enough to go with going from MD <-> CPLD <-> EEPROM

/WRH
/AS
/ASEL
Will remain unconnected to the CPLD.


You guys mentioned earlier that /AS is not asserted for DMA, and that /CAS2 is asserted for DMA. But do you guys know if /CAS0 is also asserted for DMA? If /CAS0 is asserted for all accesses (68k, Z80 and VDP), then I can get the CPLD to listen using /CEO and /CAS0 and therefore have more time to get the data from the EEPROM sorted.
Otherwise I will need to use /CEO and /CAS2, but that will give me less time.

Also from more reading on Expansion Port Signals https://gendev.spritesmind.net/forum/vi ... php?t=1563 it appears that I just need to have the access faster than 150ns if relying on /CEO and /CAS0. So 130ns should be fast enough, if using those signals.

HardWareMan
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Re: Cart Design Questions

Post by HardWareMan » Mon May 27, 2019 2:13 pm

themrcul wrote:
Mon May 27, 2019 7:00 am
You guys mentioned earlier that /AS is not asserted for DMA, and that /CAS2 is asserted for DMA. But do you guys know if /CAS0 is also asserted for DMA? If /CAS0 is asserted for all accesses (68k, Z80 and VDP), then I can get the CPLD to listen using /CEO and /CAS0 and therefore have more time to get the data from the EEPROM sorted.
All the cards use CE0 and all of them works fine with DMA. The main problem with CE0 is a bouncing on some early hardware revisions. That causing a problem with emulated memory on SDRAM since it required going throug some stages with stable address and that address must be captured asap. Fully static memory (RAM or ROM) can handle with it if changing address delay still less then CAS2 duration.

themrcul
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Re: Cart Design Questions

Post by themrcul » Tue Jun 04, 2019 4:11 am

Great, thanks for that. I have dropped the /AS line and am using /CAS2 now.

I have finished the first version of the schematic now (with a linear power regulator for voltage regulation), ready for drawing a PCB layout from. You guys have been so helpful to me for this project. I am in your debt.

One question I now have is about power regulation.

I have searched to find out how much power is available to me at the cartridge to spend on CPLDs, FPGAs, MCUs, etc. The best I can find is that Virtua Racing consumes 120mA from the cart, and that is much higher than standard games due to the extra chip on board.
So, logically it is probably not a great idea to go much beyond that power budget.

In terms on the devices I have on board, they are with their estimated power consumption:
1x SAM4S (30mA @ 3.3V) (50mA startup current needed)
1x Intel Max V CPLD (VCCIO 10mA @ 3.3V (40mA startup current), VCCINT ~10mA @ 1.8V)
1x EEPROM @ 50mA
Audio lines need 33mA @ 5V x 2 for stereo, I'm not sure about how much power is lost to heat from the LM4880 op-amp. I can't determine this from the datasheet, for this device or any other op-amp I've surveyed for this project either.
3x SN74ALV transceivers for 5V<->3.3V voltage conversion (I can't determine their power consumption from the data sheet so I am led to believe the power consumption is low).

So in all, the load on the regulator for 5V->3.3V is 50 + 40 + 50 = 140mA (not including the 3x SN74ALVs)
That in addition to needing 75mA for the audio amplification. So this is now more than double what Virtua Racing needed.

At first I was thinking of using a linear power regulator for ease of use, few needed parts and cheap cost, however I have recently read that they are very inefficient and can burn lots of energy into heat, particularly if the change in voltage is high (which it is in the case of 5V->1.8V).

Would you guys therefore recommend a Buck Switching Regulator instead for higher power efficiency? The cost is not significantly higher, but it does require more parts (it needs 4 different resistors and 2 different inductors, along with the input and output capacitors).

Do you guys have any thoughts on power regulation and consumption for a Mega Drive PCB project?

Thanks again in advance.

HardWareMan
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Re: Cart Design Questions

Post by HardWareMan » Tue Jun 04, 2019 10:29 am

themrcul wrote:
Tue Jun 04, 2019 4:11 am
In terms on the devices I have on board, they are with their estimated power consumption:
1x SAM4S (30mA @ 3.3V) (50mA startup current needed)
1x Intel Max V CPLD (VCCIO 10mA @ 3.3V (40mA startup current), VCCINT ~10mA @ 1.8V)
1x EEPROM @ 50mA


So in all, the load on the regulator for 5V->3.3V is 50 + 40 + 50 = 140mA (not including the 3x SN74ALVs)
That in addition to needing 75mA for the audio amplification. So this is now more than double what Virtua Racing needed.
You shouldn't use linear regulator (any 1117 like). Only DC-DC step down. Then, the result current will be only approximately 100mA (50mA@3,3V=165mW, 40mA@3.3V=132mW, 10mA@1.8V=18mW and 50mA@3.3V=165mW, in total 165+132+18+165=480mW, or 0.480W/5V=96mA, plus DC-DC efficiency losses about 5%-6%).

themrcul
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Re: Cart Design Questions

Post by themrcul » Tue Jun 04, 2019 10:36 am

Thanks HardwareMan that's what I thought - I'll need the efficiency of a step-down regulator rather than a linear regulator. I'll fix up the schematic.
Sadly the only parts I found that had the parameters I want is in a WFDFN package, so I'll need to use a hot air gun for the first time to get it onto the board.

themrcul
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Re: Cart Design Questions

Post by themrcul » Tue Jul 09, 2019 2:02 am

Hey fellas,
After hours and hours of learning, researching, reading spec sheets, etc and selecting components I believe I have a workable design on my hands.

This is a debug board that has a USB port from which I aim to be able to write to the EEPROM with, without needing to unplug the cart and plug it into a second device to write to the EEPROM. This EEPROM is also pin-compatible with an SRAM chip I have my eye on for future developments!

As such it needed an extensive redesign and a much beefier CPLD (144 lines compared with 100 for a 16-bit design or a 64 line one for an 8-bit design).

I built it a week or so ago but then realised if I rotate the CPLD around a bit more I could get a better path for a clock output from the ARM to the CPLD, in case I want or need to do that. So I did *another* rebuild.

I also had enough space and spare lines to squeeze an LED and push switch to the ARM, which should help with debugging things.

It has an LM4880 250mA op-amp, which should push 35mA on each channel into 75ohms, which is just enough (hopefully!) I have some potentiometers on the board in place of the voltage divider feedback resistors so I can measure and determine what the op-amp should be amplifying to before it distorts on the Mega Drive. After I've worked out those resistor values I can replace the potentiometers with plain ressistors for the finalised board, along with downsizing the CPLD, removing the push button and LEDs, etc.

My signal lines are 5.4mil, power pins on ICs are 0.25mm, power delivery lines to copper fill areas are either 0.6mm or 1mm.

The board runs 4 voltages - 5V main power, 3.3V signal level for devices, 1.8V core voltage for the CPLD and 1.2V core voltage for the ARM chip. The arm chip has it's own voltage regulator thankfully so I am getting away with two voltage regulators on the board.

Side B:
B Side.PNG
B Side.PNG (175.45 KiB) Viewed 1706 times
Side A:
A Side.PNG
A Side.PNG (89.67 KiB) Viewed 1706 times
3.3V net highlighted: (I don't know why the second bypass caps aren't highlighted, I'll check to make sure they are connected when I get home)
3.3V.PNG
3.3V.PNG (167.84 KiB) Viewed 1706 times

themrcul
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Re: Cart Design Questions

Post by themrcul » Tue Jul 09, 2019 2:04 am

1.8V net highlighted:
1.8V.PNG
1.8V.PNG (168.55 KiB) Viewed 1706 times
1.2V net highlighted:
1.2V.PNG
1.2V.PNG (168.46 KiB) Viewed 1706 times
3D render 1 (note I couldn't find 3D models of all components, but it still gives me a good idea of what it will look like in the end):
3D B.PNG
3D B.PNG (126.66 KiB) Viewed 1706 times

themrcul
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Re: Cart Design Questions

Post by themrcul » Tue Jul 09, 2019 2:06 am

3D render 2 (A side):
3D A.PNG
3D A.PNG (37.08 KiB) Viewed 1706 times
Doing this project has been the most fun I've had in a while!

TmEE co.(TM)
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Re: Cart Design Questions

Post by TmEE co.(TM) » Tue Jul 09, 2019 2:17 am

You should use multiple vias for the power traces whenever possible. Looking good otherwise ~
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