MD-NICCC - a 3D Mega Drive experience by TiTAN

[Sik]

Yes, you do. MD has more VDP bandwidth than the SNES homonym, nearly twice if my memory serves me well. They even go to only 50hz (PAL) to maximize it.
That's what really counts on this demo.

Um, wrong, even assuming H40, the bandwidth is only somewhat larger (around 7KB vs around 6KB, if memory serves well), and in H32 they're practically identical. If the Mega Drive had been equipped with 128KB of VRAM you'd be right since in that mode it does indeed double bandwidth :​P Alas…

But yeah, even that considered, PAL is a completely different beast than NTSC, it has over twice as much vblank time and transfer bandwidth during vblank is proportionately larger (at the expense of lower framerate).

In this demo, after some educated guesses, I believe border tiles are pre-rendered and solid tiles use the background color to avoid transfers. Some times you can see in the distance when the overall color changes.

Nah, the original demo already changed all 16 colors at a whim (and a lot of the glitchy polygons came from there too, though the format containing non-convex polygons didn't help matters).

That said, there are pre-built solid tiles for all 16 colors (rather than just background color), which is indeed what's being used to fill in the large solid areas.

[Miquel]

You have made me see it again. I settle for:
- A rough approximation with solid tiles in one plane
- Pre-rendered sprites for the borders

Again, it’s all about transfers.

[TmEE co.(TM)]

MD and SNES VRAM bandwidths are very similar in H256, though in H320 MD will pull ahead a bit and on DMA bandwidth alone both should be fairly similar, within 10% probably, be them both in 50 or in 60Hz. But here we see more than twice speed difference.

[Miquel]

Um, wrong, even assuming H40, the bandwidth is only somewhat larger (around 7KB vs around 6KB, if memory serves well), and in H32 they're practically identical. If the Mega Drive had been equipped with 128KB of VRAM you'd be right since in that mode it does indeed double bandwidth :​P Alas…

But yeah, even that considered, PAL is a completely different beast than NTSC, it has over twice as much vblank time and transfer bandwidth during vblank is proportionately larger (at the expense of lower framerate).

Then VDP reads bytes during DMA? instead of words. I remember somewhere on the manual saying it reads words... (?)

The point is SNES has a 8bit data bus, while MD has one of 16bit; should be twice as fast for similar memory speed.

[Sik]

The VRAM equipped on the Mega Drive is 8-bit though, so VRAM writes take twice as long as CRAM and VSRAM writes do. That's precisely why 128KB VRAM would have been awesome: what that mode does is set the VRAM bus to 16-bit instead, which in turn doubles the bandwidth (not just the available memory). But they decided to not equip enough memory for that on the Mega Drive (probably to cut down costs), so we're stuck with the slower mode.

Unless somebody wants to make a tech demo that only works on a Tera Drive ;P (or modded Mega Drives)

[Stef]

Pretty sure Sik is talking about the SNES port of the ST-NICC demo which was also released at Revision this year.

Oh i completely missed it... i really wonder why they needed the SFX here, probably doing the polygon rendering from the SFX.
I don't know how much they are close to the original vertex format or if they are closer to a video / image data streamer.

[bioloid]

this one too https://demozoo.org/productions/202901/

[Miquel]

Um, wrong, even assuming H40, the bandwidth is only somewhat larger (around 7KB vs around 6KB, if memory serves well), and in H32 they're practically identical. If the Mega Drive had been equipped with 128KB of VRAM you'd be right since in that mode it does indeed double bandwidth :​P Alas…

SNES runs at 2 speeds, 2.68 by default and in some directed cases at 3.58 mhz; that is MD is 30% faster and 6% respectively at accessing memory.

It seems they did a mapping mess when trying to do snes compatible with nes, later they drop compatibility but not the mess.

[Stef]

No, the 7.67 Mhz 68000 is actually *slower* than the 2.68 Mhz 65C816 at accessing memory... it's why the 65C816 can work at 2 speeds, fast memory (ROM) were too expensive in 1990 so they voluntary limited it to 2.68 Mhz to reduce cost on RAM (which is fixed to work at 2.68 Mhz) and to maintain acceptable cost on ROM too (while leaving possibility to increase ROM speed later when chips would become cheapers).
The VDP DMA does access MD memory at almost the same speed than the SNES one though (but we have 16 bit memory on MD while we have 8 bit memory on SNES).

[Chilly Willy]

You have to remember that the 68000 takes multiple clock cycles to access memory (generally 4 clocks), while 65xx variants take 1 cycle. However, the 65xx cannot transfer memory on every clock, so that's moot. Also remember that the SNES uses a BYTE bus for data while the MD uses a WORD bus, so the MD does indeed transfer data from the cart much faster than the SNES, even in fast mode.

[Miquel]

I’m sorry but how the hell can a memory be accessed in only 1 cycle?!? You need two cycles at minimum, one to put the address to the address bus, and then another to retrieve data from data bus.

For example a NOP takes 2 cycles on a 65816, that sounds correct if there is prefetch.

Something is wrong here, either misinformation or cycles need to be doubled.

[TmEE co.(TM)]

http://laughtonelectronics.com/Arcana/V ... iming.html

[Miquel]

I'm sorry Chilly Willy, you were saying exactly what I think, I just read "read memory of 1 cycle" and go berserk.

The data is ready at the end of the first cycle, but can't be used until next cycle; so it's two cycles from my point of view.

[TmEE co.(TM)]

One edge puts address on the bus, other edge collects the data. One clock cycle.

[Stef]

The 6502 uses 2 phases cycle, so first half cycle is used to set address while second half is use to read/write value.