New Documentation: An authoritative reference on the YM2612

[Mamizou]

Are the lower 4 bits dropped of the 14bit output or something else happens ?

Yeah, they're just dropped. If you look where I have the truncation labelled, you'll see 14 bits coming out of the Sine+EG adder, but 4 of those traces just end. It's too bad they couldn't add a serial output pin so you could just serialize that 14-bit data and send it to an external DAC like other OPN series chips, although you wouldn't get the PCM data. And I guess you'd just use an OPNA or OPM anyway.

Also, the sine ROM is exponentiated so they could just use an adder and no multiplier unit...
How is the PG freq multiplication with MUL parameter handled ?

MUL is still handled in the PG. I haven't figured out the techniques for that yet.

[TmEE co.(TM)]

I report that my FM core is modulating, PG and OP work great !
My EG is still not quite right, the attack part behaves wrong but I am getting it fixed up soon !
Then I will add LFO and SSG-EG... latter will ruin my pretty code haha

[GManiac]

Here's my very old and abandoned YM emu in Delphi, if you are interested, with some comments in Russian.
http://shedevr.org.ru/ghost/ym2612/YM_Emu.rar
What is not implemented: SSG-EG, special 3ch mode.

[TmEE co.(TM)]

Your algos are implemented in a very close way to mine hehe

[Nemesis]

I'll actually be finally releasing my emulator soon. I'm currently targeting the end of March for the first release. I'm going to be releasing the sourcecode very soon afterwards. I built the YM2612 core in my emulator while I was doing these tests, and each aspect of its implementation was tested in hardware, so the sourcecode for it should be a good reference for anyone trying to build a YM2612 core in the future. There are a lot of comments in there clearly stating what's been backed up by hardware tests, and why particular areas are implemented in certain ways.

[neologix]

I built the YM2612 core in my emulator while I was doing these tests, and each aspect of its implementation was tested in hardware, so the sourcecode for it should be a good reference for anyone trying to build a YM2612 core in the future.

AWESOME SAUCE.

[TmEE co.(TM)]

My envelopes look perfect now, real chip progresses same way and Kega Fusion too.
I also had operator order problem but I fixed that hoping it also fixes the modulation problem I had but that did not happen. Unmodulated outputs are perfect though.

I take the final 14 bit output of an operator, shift it right 4 places and add to other operator's 10bit phase output value. I tried several bit positions but that really did not help make right sound...
Maybe I am missing something simple ...?

[GManiac]

14-bit operator output sums with other operators's output, if it is present (algos 1-3), then their sum shifts RIGHT for ONE bit and this value is added to input phase of modulated operator. No exceptions.
For feedback fb1 and fb2 are summed, then value shifted for various amount of bits, it depends on feedback depth. Yes, there are really two feedback registers, I made it sure by special tests.

[andlabs]

Here's my question.

I am trying to write a concurrent emulator (rather than a sequential one like existing emulators) that tries to mimic the chip operation on some level. I'm confused as to how the EG is supposed to work if it runs at 1/3 the clock rate of the rest of the chip, since each operator is updated on each clock cycle, not every 3 clock cycles. Is there some value caching going on? Thanks.

http://github.com/andlabs/ym2612 is the code I have so far btw; I never bothered to ask if I could use Nemesis's algorithms so I guess I'll ask now =P I only put this up because I thought I was going to change OSs and didn't want to lose anything, but didn't at the time

[TmEE co.(TM)]

YM chip IS sequential for the most part.

The EG has an output and it is used 3 times by other parts while it is not updated. Updates happen every 3 cycles.

[andlabs]

Right, sequential isn't exactlyt he right word, but componentized/concurrent rather than singlethreaded and linear? Whatever it may be I'm trying to imitate the chip as much as possible given the limited knowledge I have (how do you read a die shot?)

So let me get this straight: there are 24 outputs (one for each operator) and the operator unit just picks the appropriate one for the current channel?

[TmEE co.(TM)]

These 24 outputs are also the "accumulators" of all envelope calculations.

[andlabs]

Ok. So in that case (and this may have been answered already but just to be sure), are all EG outputs updated at once on the three-cycle mark, or does it update each operator EG in a three cycle loop? Or to put it in code terms, is the EG unit loop

Code: Select all

for each clock pulse {
    send out current operator's EG output // I know this isn't literally what the hardware does but eh
    if three cycles passed {
        recalculate all EG outputs
    }
}

or

Code: Select all

for each clock pulse {
    send out current operator's EG output
    do 1/3 of the operation for the current EG output being calculated // oversimplification of what actually is going on but you get what I mean
    if done calculating this EG output {
        go to next
    }
}

Thanks.

[TmEE co.(TM)]

I wait for 3 cycles to pass (or for a special SSG-EG condition) and then update all operators and channels at once. I don't think the chip behaves any different, it makes no sense to have a counter for each channel separately, the effect of that would be inaudible.

I found one new problem in my FM core -
I was adjusting feedback and then I saw that my sawtooth looked like this :

Code: Select all

|\   |\
| \  | \
  | /  | /
  |/   |/

instead of this :

Code: Select all

|\   |\
| \  | \
|  \ |  \
|   \|   \

Bottom halves of my waveform are horizontally flipped. I never saw it as sines are all really symmetrical
Fixing this problem should fix all my modulation related issues.

EDIT : I forgot to add sign to the modulation value

[GManiac]

Somewhere was an opinion that envelopes of different channels of one block (block = 3 channels) are updated in different cycles of 3-cycle phase. I think it's true because update requires time. I mean:
Global cycle 1: channels 1 and 4 updated
Global cycle 2: channels 2 and 5 updated
Global cycle 3: channels 3 and 6 updated

Global cycle 4: channels 1 and 4 updated
...

Also note that global EG counter max value is 4095, not 4096, so full EG "cycle" lasts 12285 internal cycles.