68000 micro-instructions documents?

For hardware talk only (please avoid ROM dumper stuff)
eteream
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68000 micro-instructions documents?

Post by eteream » Tue May 03, 2011 10:17 pm

Is there a way to know what 68000 does exactly in every cycle?

I mean, there are some things (PC++, decode instruction) that can be done not only in specific cycle but in 1 or 2 more.

Take, for example the nop instruction, 4 cyles. Yon can do the PC:=PC+1 in the 3rd o 4th cycle. Same goes for the decode operation.

So, are there 68000 micro-instructions documents? thanks!

HardWareMan
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Post by HardWareMan » Wed May 04, 2011 12:04 am

You do not have enough M68KPM and M68KUM?

Chilly Willy
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Post by Chilly Willy » Wed May 04, 2011 12:29 am

I'm not aware of any documentation of what the 68000 does in each state. The closest I've seen is docs on how certain instructions "prefetch" the next instruction and how that affects the operation of the current instruction and the next instruction. Said info can be found via google.

HardWareMan
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Post by HardWareMan » Wed May 04, 2011 3:56 am

Look at this.

TascoDLX
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Post by TascoDLX » Wed May 04, 2011 6:25 am


Chilly Willy
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Post by Chilly Willy » Wed May 04, 2011 9:37 pm

That second patent really covers the internals. Of course, it comes from a time when patents were still valid inventions. You won't find anything close in a modern patent - the lawyers wouldn't stand for it. :lol:

eteream
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Post by eteream » Thu May 12, 2011 6:28 pm

HardWareMan wrote:You do not have enough M68KPM and M68KUM?
Are these HLD dessigned CPUs? There is nothing about these words searching in Internet.
Chilly Willy wrote:I'm not aware of any documentation of what the 68000 does in each state. The closest I've seen is docs on how certain instructions "prefetch" the next instruction and how that affects the operation of the current instruction and the next instruction. Said info can be found via google.
HardWareMan wrote:Look at this.
Here explains while cpu is executing an instruction also is decoding next instruction and fetching next next opcode. Not enough, but thanks!
TascoDLX wrote:If you're serious about it:

US Patent 4,307,445 - Microprogrammed control apparatus having a two-level control store for data processor
US Patent 4,325,121 - Two-level control store for microprogrammed data processor

I doubt you'll find anything more specific
I'm absolute serious with my will to learn about it. Do you find some joke here? :)
The 2nd one is really, really interesting... lots of info waiting to be decrypted. THANKS!
Chilly Willy wrote:That second patent really covers the internals. Of course, it comes from a time when patents were still valid inventions. You won't find anything close in a modern patent - the lawyers wouldn't stand for it.
But that is a little hilarious, the idea is to prevent copying.

Anyway, that's what I get from official document, the last patent and my own guesses:

Image

There are some things uncovered in the 4,325,121 for example the damn PC:=PC+1, I really don't know how to fit it in this design without adding and extra adder.

And how the RESET and HALT perform. For instance, if a read is performing and you stop immediately the CPU the external buses will be busy while halt is active. I think that this is not desirable.
Then, reset and halt allow the completion of the current operation or micro-instruction?

Chilly Willy
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Post by Chilly Willy » Thu May 12, 2011 9:27 pm

eteream wrote:
Chilly Willy wrote:That second patent really covers the internals. Of course, it comes from a time when patents were still valid inventions. You won't find anything close in a modern patent - the lawyers wouldn't stand for it.
But that is a little hilarious, the idea is to prevent copying.
Which defeats the whole purpose of a patent. A patent is an agreement with the government where you agree to teach the average practitioner of your field of endeavor how to make something in exchange for an exclusive right over said thing for a set period. To write a patent in such a way as to prevent copying is not holding up your end of the deal, and the patent SHOULD be invalidated. That's my biggest complaint about modern patents - lawyers make them nearly impossible to understand, and once you do, there's nothing in the patent but some vague hand-waving. 99% of all patents issued in the last decade should be invalid for that reason alone.

TmEE co.(TM)
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Post by TmEE co.(TM) » Fri May 13, 2011 6:06 am

eteream wrote:
HardWareMan wrote:You do not have enough M68KPM and M68KUM?
Are these HLD dessigned CPUs? There is nothing about these words searching in Internet
68K User Manual and 68K Programmers Manual :P
Mida sa loed ? Nagunii aru ei saa ;)
http://www.tmeeco.eu
Files of all broken links and images of mine are found here : http://www.tmeeco.eu/FileDen

TascoDLX
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Post by TascoDLX » Fri May 13, 2011 1:34 pm

eteream wrote:There are some things uncovered in the 4,325,121 for example the damn PC:=PC+1, I really don't know how to fit it in this design without adding and extra adder.
That's exactly what you should be doing. Are you generalizing the execution unit into a single ALU?
In FIG. 3, a simplified block diagram of execution unit 22 (in FIG. 2) is shown. The execution unit is a segmented two-bus structure divided into three sections by bidirectional bus couplers. The left-most segment contains the high order word for the address and data registers and a simple 16-bit arithmetic unit. The middle segment contains the low order word for the address registers and a simple 16-bit arithmetic unit. The right-most segment contains the low order word for the data registers and an arithmetic and logic unit.
In general, the PC increment is handled by the 16-bit arithmetic units w/ carry, leaving the ALU free for other stuff.

For a more detailed look at the execution unit:

US Patent 4,296,469 - Execution unit for data processor using segmented bus structure

HardWareMan
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Post by HardWareMan » Sat May 14, 2011 5:04 am

I don't get it: what a problem with PC incrementation? If you decided to do hardware design, you have to forget almost all the things you learned in programming. Seriously. Tell me, why do you PC a separate register with adder when it can be designed as a counter with loading? And EA you will still be calculate in main ALU during the execution of opcode. Generation "next" detected. :3

eteream
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Post by eteream » Sat May 14, 2011 7:33 pm

Chilly Willy wrote:
eteream wrote:
Chilly Willy wrote:That second patent really covers the internals. Of course, it comes from a time when patents were still valid inventions. You won't find anything close in a modern patent - the lawyers wouldn't stand for it.
But that is a little hilarious, the idea is to prevent copying.
Which defeats the whole purpose of a patent. A patent is an agreement with the government where you agree to teach the average practitioner of your field of endeavor how to make something in exchange for an exclusive right over said thing for a set period. To write a patent in such a way as to prevent copying is not holding up your end of the deal, and the patent SHOULD be invalidated. That's my biggest complaint about modern patents - lawyers make them nearly impossible to understand, and once you do, there's nothing in the patent but some vague hand-waving. 99% of all patents issued in the last decade should be invalid for that reason alone.
You are absolutely right in an ideal world. But in this one, every country has his own laws about intellectual rights, even may be there are some without. For example typical communism has no enterprises so there is no need for them. May be i'm wrong, if so let me know.
HardWareMan wrote:I don't get it: what a problem with PC incrementation? If you decided to do hardware design, you have to forget almost all the things you learned in programming. Seriously. Tell me, why do you PC a separate register with adder when it can be designed as a counter with loading? And EA you will still be calculate in main ALU during the execution of opcode. Generation "next" detected. :3
I'm really glad to listen that sort of things, but there is no need to go to personal matters (may be i'm a lot more old than you :P). You are right about PC inc. BUT your forget one thing, when you are calculating the EA you are not executing anything!
Every 68K instruction works in this way LOAD_MEM+EXEC(ALU+FETCH)+STORE_MEM.
For example: MOV (A0), (A1) takes 4+4(2+4)+4 cycles. So there is no overlap between LOAD_MEM, EXEC or STORE_MEM.
Notice that EA is needed on the falling edge of the first cycle of LOAD_MEM or STORE_MEM, 3 cycles away of EXEC phase.
If you have to say something about "next generation", I'm here to listen. :D

HardWareMan, if you give me some days I can make diagrams to illustrate it.
TascoDLX wrote:
eteream wrote:There are some things uncovered in the 4,325,121 for example the damn PC:=PC+1, I really don't know how to fit it in this design without adding and extra adder.
That's exactly what you should be doing. Are you generalizing the execution unit into a single ALU?
In FIG. 3, a simplified block diagram of execution unit 22 (in FIG. 2) is shown. The execution unit is a segmented two-bus structure divided into three sections by bidirectional bus couplers. The left-most segment contains the high order word for the address and data registers and a simple 16-bit arithmetic unit. The middle segment contains the low order word for the address registers and a simple 16-bit arithmetic unit. The right-most segment contains the low order word for the data registers and an arithmetic and logic unit.
In general, the PC increment is handled by the 16-bit arithmetic units w/ carry, leaving the ALU free for other stuff.

For a more detailed look at the execution unit:

US Patent 4,296,469 - Execution unit for data processor using segmented bus structure
You get it. I'm simply romantic about the simplicity of the 68K.
TascoDLX wrote:Are you generalizing the execution unit into a single ALU?
I'm not sure you're referring to. I know that 68K uses two 16bit ALUs instead of 1 of 32bits. If you don't agree with sharing ALU with data and addresses: as I said earlier they don't overlap. To fetch only PC register is needed, no ALU operation occurs.
If you want to say is that ALU and shift operations are separated, well, I merged them.

TascoDLX
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Post by TascoDLX » Sun May 15, 2011 3:13 am

eteream wrote:I'm not sure you're referring to. I know that 68K uses two 16bit ALUs instead of 1 of 32bits. If you don't agree with sharing ALU with data and addresses: as I said earlier they don't overlap. To fetch only PC register is needed, no ALU operation occurs.
If you want to say is that ALU and shift operations are separated, well, I merged them.
I was referring to the fact that the 68K uses one 16-bit Arithmetic Logic Unit, plus two additional (but limited) 16-bit Arithmetic Units -- one operates on the registers' low 16 bits and the other on the registers' high 16 bits. The two limited arithmetic units are not much more than adders, but they are widely used for EA calculation and PC & SP manipulation.

The overall design allows for all three units to operate for the same nanoinstuction, though not very often of course. The only reason I mention it is because it is quite important if you want to understand the microcode/nanocode. But, you can draw the diagram any way you want. :wink:

eteream
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Post by eteream » Fri May 20, 2011 2:12 pm

If you help me find which one micro/nano-instruction you need all the 3 units working altogether it will be very helpful.

May be you like this ones a little bit more:

Image
Image

TascoDLX
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Post by TascoDLX » Sat May 21, 2011 12:32 pm

eteream wrote:If you help me find which one micro/nano-instruction you need all the 3 units working altogether it will be very helpful.
Well, there are definitely more than one. In many cases, the ALU executes some value AND -1 in order latch the value while the AU does something like PC+2. It's all a matter of reusable micro/nanocode. If you want to understand the nanocode, you really should read the patent. It explains the nanocode diagrams quite nicely, despite a few typos.
eteream wrote:May be you like this ones a little bit more:
I get the impression that you're redesigning the CPU. Awesome. I'd love to hear all about it. :wink:

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