New Documentation: An authoritative reference on the YM2612

[Nemesis]

Ehh, for posterity, I'm going to elaborate anyway. The test I just posted uses a single operator from each channel. The phase generator is frozen, with the phase generator outputting a maximum positive value each cycle. The envelope generator for the selected operator in each channel is locked in an infinite decay phase, at an effective internal attenuation value of 0. A different TL value is used for the selected operator in each channel. The overall effect of this is that each channel has a constant output. The attenuation level that each channel sits at is controlled by TL.

The screenshot I posted shows the output from the YM2612, sampled directly from the chip with an oscilloscope. If all the channels were summed, and the gaps were gaps between successive samples, every sample would be the same value. As you can see, the levels between each successive sample differ, with each sample clearly representing a different channel with a different attenuation value, as set by TL. Here's another screenshot I've just taken:


This one shows both the left and right channels, and this time, I've used unique values for TL in each channel, moving from 0x0 to 0xA with a step of 2 from channel 1 to channel 6. Channel 1 is the one mostly visible on the lefthand side. You can see how the channels are actually output out of order. The apparent output order is 1,5,3,2,6,4. Also, according to this, the left and right output streams are actually output at the same time, which I find a little surprising.

In terms of the frequency the DAC would have to run at, if we assume the YM2612 does use an embedded YM3016, if it was only doing a single channel, the YM3016 would need to be running at a minimum clock rate of around 5.07MHz, which is above its reported maximum clock input of 5MHz. This does suggest the YM2612 may be using a different DAC. It's also possible it uses two DAC's, one for the left channel, and one for the right channel, and controls them both in parallel. At any rate, it does appear that the YM2612 does its DAC conversion quite differently than the known OPN chips that have an external DAC, like the YM2608.

[HardWareMan]

Whoa... Channel order is not "123456"? As for multiplexing output, I had already say: 6 timeslots per one channel (left and right). That's is why DAC function replace one of channel (number 6). Nemesis, please make measurement of time (frequency) between start of every timeslot and time of width of one timeslot.

[Snake]

ARGH pictures too big, lots of scrolling...

Ok, your pictures are interesting.

I did do similar tests many years ago, using equipment owned by a guy I worked with. I didn't see the same results. Maybe his equipment wasn't good enough. Maybe this was changed in later chips. I don't know now. Still...

The operators/channels take care of themselves. The function of the accumulator is, absolutely, to sum the channels. If it's not doing that it actually suggests they REMOVED the accumulator. They did exactly this (and it's documented) in some simpler chips, but the YM2612 sounds much cleaner.

the left and right output streams are actually output at the same time, which I find a little surprising.

They will be, it's a stereo DAC.

In terms of the frequency the DAC would have to run at, if we assume the YM2612 does use an embedded YM3016, if it was only doing a single channel, the YM3016 would need to be running at a minimum clock rate of around 5.07MHz

I make it 5.11MHz (and twice that if, as you originally suggested, it did 12 passes) - but it's probably more than that because the chip requires some time to do the actual conversion and settle.

This does suggest the YM2612 may be using a different DAC.

Yes, I mentioned this before. I knew it was a different DAC, but it seems very odd that they would put a faster DAC in there instead of an accumulator.

In any case, I still say this isn't the reason for the distortion we are hearing. Just as well, because any way you try to downsample that it's just going to sound pretty much the same as if they were mixed. Only playing it at the same frequency is going to sound the same.

[Nemesis]

Whoa... Channel order is not "123456"? As for multiplexing output, I had already say: 6 timeslots per one channel (left and right). That's is why DAC function replace one of channel (number 6). Nemesis, please make measurement of time (frequency) between start of every timeslot and time of width of one timeslot.

I can go one better than that:


This is the analog output from the YM2612 next to the master clock (7.61MHz or there abouts). As you can see, there are 24 master clock cycles between each timeslot. The silence gap is most likely at the start of the timeslot, and represents the period in which the accumulator is sending the serial data stream to the DAC. Looking at the bus communication diagram in the YM3016 datasheet, with 16 bits of data to stream, that's 16 cycles used for the data transfer, plus an extra 2 cycles, one before the start of the stream, and one after the end of the stream, for the data latch input, plus an extra 1 cycle before the final latch input, where the SMP1/2 lines are negated. That gives 19 cycles for the serial communication, which is the observed gap of silence between each output, leaving only 5 cycles for the output to remain asserted across a full clock cycle, which is exactly what we see on the image above.

Tying this back into the clock rates used in the YM2612, the DAC has one timeslot per channel, or 7610000/6/4=317083, where 6 is the fm prescaler, and 4 is the number of operators per channel. The actual DAC runs at the full input clock rate. Oh, and based on the datasheet for the YM3016, it looks like both channels can be programmed at once on that device (IE, the DAC can latch a single output stream and send it to both channels), and seeing as the communication between the accumulator and the DAC seems to match the communication pattern of the YM3016, it seems the embedded DAC is most likely a YM3016 derivitive. Since this embedded DAC is obviously running at 7.61MHz however, it must support a higher clock input. The YM3016 was only rated for a max of 6MHz (not 5MHz like I said earlier, that was the YM3015. Perhaps this would make the DAC model a YM3018?).

EDIT: Some googling seems to confirm that the YM3018 does exist, but there seems to be absolutely no information on it.

[Snake]

it seems the embedded DAC is most likely a YM3016 derivitive.

Well, as I mentioned before, I read somewhere (fucking wish I could remember where) that it's only 9 bit. That would seem to make more sense now, wouldn't it? No point in putting a full 16-bit capable DAC in there if it's not going to get used.

That channel order is fucking strange, though.

[HardWareMan]

Whoa! This is a very accurate data. So, one timeslot takes 24 of VCLK. So, all 6 channel takes VCLK/24/6. In case of VCLK=7.61MHz it will be 7600KHz/24/6=52kHz... Mmmm... That is more than twice faster, than I thought...

[Nemesis]

Well, as I mentioned before, I read somewhere (fucking wish I could remember where) that it's only 9 bit. That would seem to make more sense now, wouldn't it? No point in putting anything better in there if it's not going to get used.

Anything's possible. I must admit, I thought the YM2612 wasn't doing too much differently in terms of the DAC, despite the fact this one is embedded. Guess I was wrong. Different precision on the input is certainly possible. The circuitry of the DAC itself could also be very different, and there could well be errors in it as you suspect, or they might have taken some shortcuts to reduce complexity or power requirements. It's a fair bet this DAC was built, or at the very least customized, for the YM2612.

That channel order is fucking strange, though.

Yeah, I don't get that either.

[Snake]

It might be interesting to try this on an MD2 and see if theres any differences. Not that it probably makes much difference in emulation, but still...

[Nemesis]

I haven't modded a MD2 to sample direct from the YM2612 output. Let me grab one off the stack and see what I can rig up.

[Snake]

Oh, and incase it's of interest - the YM2413 is the chip that has no accumulator... and also an embedded 9 bit DAC. Isn't that interesting.

Let me grab one off the stack

Heh, how many have you got?

[Nemesis]

Oh, and incase it's of interest - the YM2413 is the chip that has no accumulator... and also an embedded 9 bit DAC. Isn't that interesting.

Hmm, maybe I can get my hands on one a run some tests on that. Comparing the two might help answer some questions. Hell, maybe I can put one in the Mega Drive in place of the YM2612.

Let me grab one off the stack

Heh, how many have you got?

I honestly don't know. It seems like every time I move something or look in a box I haven't opened in awhile, I find another one hiding. O_o I bought too much Mega Drive stuff on ebay.

[Snake]

Hmm, maybe I can get my hands on one a run some tests on that. Comparing the two might help answer some questions. Hell, maybe I can put one in the Mega Drive in place of the YM2612.

Doubtful, the chip is very different. But it's the chip used in the Japanese SMS. Go on, now tell me you've already got one

Just done some googling and found:

- OPLL: Budget version of the OPL2. It's quite cut down, and can only have 1 fm patch at the same time - the other sounds must come from a ROM that has 15 different FM sounds. Also lacks an accumulator (channels are summed together with an analog filter instead).

from http://www.soundshock.se/phpBB2/viewtop ... f8d5c#2280

OPLL=YM2413.

[TmEE co.(TM)]

YM2413 will not start working in place of YM2612 unless you make code exactly for the YM2413... the pinout is very different aswell.

I'm looking forward to seeing some more info about MD2 sound

And by judging from aliasing noise, things do sound like the DAC is 9 or 10 bits...

[Snake]

While we're waiting for Nemesis to do the tests, thought I'd post my thoughts on the distortion.

If you've ever looked at the waves produced, it seems as though one side performs exactly as it should, and hits silence when it should. But the other side doesn't, producing a non-sinewave. it takes much longer to get to zero, and it distorts on the way there.

It's been a long time since I've done any tests on this at all (5 years probably), but I've been thinking about it a fair bit recently. I *think* it's the negative side that has the problem (I'm sure somebody here can confirm), and if so, it would seem to indicate the chip handles negative samples incorrectly, OR that the values are scaled before hitting the DAC, and there is a problem with scaling negative values.

The standard yamaha DACs, as far as I remember, don't use 2s compliment, but I'm pretty sure the operators do, so theres another possible conversion that could go wrong.

It's also possible it's just a problem with the DAC itself, but that doesn't seem as likely, because the error is actually quite a large one.

With a decent scope and a bit of time, it should be possible to figure out exactly what's going on here. I have neither anymore, nor the capacity to run test code anymore, or I'd have done it already

[HardWareMan]

Snake, you talking about "ladder" effect? Wich present in every channel separatly.