SpritesMind.Net

Trying to diagnose a startup issue on the Genesis, so I figured I'd document what the reset signals do. There are a lot of them:

Reset signals

WRES - Active high reset signal, pressing the RESET switch shorts it to +5V. Normally held low with a pull-down resistor. No debouncing.

VRES# - To 68000 and cartridge connector, generated by 315-5364. Asserted for 128 VCLKs (Thanks Eke!) which is approx. 130ns/cycle x 128 cycles = 16.7ms. Triggered by the rising edge of either SRES (power-up reset) or WRES (reset button) being asserted.

MRES# - Directly from the RC reset circuit (R=47K, C=10uF), goes to cartridge connector.

SRES# - Output of a LM358 that compares the output of the charging capacitor on MRES# to Vref (measured at 2.0V) from the CXA1145 Vref pin. The output is 0V when MRES#<Vref and 5V when MRES#>= Vref.

FRES - Active high reset signal. The falling edge is synchronous with SRES#. Goes to the expansion connector.

Reset button

When the reset button is pressed, VRES# is pulsed low starting a variable amount of time from the rising edge of WRES. Minimum is 2.1ms. The VRES# low pulse is always 128 VCLKs (16.7us). This means that jamming on the reset button will not send malformed reset pulses to the 68000.

Power up

When power is applied, MRES# rising edge to SRES# rising edge is about 166ms. VRES# rising edge is always 12.8ms after SRES#.

On a VA6 MegaDrive (315-5433 ASIC), the SRES# rising edge to VRES# rising edge is 98304 VCLKs (256*384) consistently.

Power down

When power is removed, SRES# falls first, then VRES# about 2.5ms later. MRES# stays high for quite a while the capacitor discharges.

In general

MRES# is the main reset signal.

SRES# is derived from MRES# and is asserted earlier than VRES#. It goes to the 315-5313, 315-5309, and 315-5364 such that these chips are reset well before the 68000 starts running. It is only asserted on a cold boot.

The 315-5364 ensures VRES# is asserted for the correct amount of time based on the SRES# and WRES inputs.

For cartridges, MRES# indicates a power-up reset (cold boot), VRES# is for both power-up and reset-button resets.

Executing a RESET instruction on the 68000 will pulse VRES# for 128 VCLKs like normal, and no other reset signals will be affected.

A circuit in the cartridge can drive MRES# low using an open collector output, which will in turn trigger SRES# and then VRES#. This will fake a cold-boot event without cycling the power.

Naiss info !

Note that the circuit reset button can be software disabled. I had cases hang games with console does not respond to the reset button, that sort of nonsense. And when activated MRES it's resets OK. Thus reset button does not make MRES signal.

What about ZRES ( which goes to Z80 and YM2612 RESET pins) ? Is it asserted with VRES when Reset Button is pressed ? Does it remain asserted until software restarts the Z80 manually ?

There is also FRES, which goes to Mega CD unit through the expansion connector, it seems to be simply an inverted SRES signal, used to reset the whole Mega CD unit.

Eke wrote:What about ZRES ( which goes to Z80 and YM2612 RESET pins) ? Is it asserted with VRES when Reset Button is pressed ? Does it remain asserted until software restarts the Z80 manually ?

Ah, that's a really good question, I'll check it in a few days and update this post.

I'll see if I can test FRES too, at least to determine when/how it is asserted in relation to the others.

I was able to test it and can confirm that, when RESET button is pressed, !ZRES is held low at the same time as !VRES and !HALT on 68k side... but remains low after that until software enables it again.

68k RESET pulse is asserted for 128 VCLK

Eke wrote:I was able to test it and can confirm that, when RESET button is pressed, !ZRES is held low at the same time as !VRES and !HALT on 68k side... but remains low after that until software enables it again.

68k RESET pulse is asserted for 128 VCLK

Aha! I didn't think to observe the reset signals against the 68000 clock -- great idea. I assumed the delays were made in an analog fashion, but clearly they have some kind of 7-bit counter here to measure that time period so precisely.

Thanks for testing these things. I don't suppose you've looked at FRES? (or maybe it isn't very interesting

Eke wrote:I was able to test it and can confirm that, when RESET button is pressed, !ZRES is held low at the same time as !VRES and !HALT on 68k side... but remains low after that until software enables it again.

This sounds quite logical, you know.

Eke wrote:68k RESET pulse is asserted for 128 VCLK

And this describes in M68KUM.

This sounds quite logical, you know.

I know it's logical, but I was playing with my new "toy" and it doesn't cost much time to confirm it

And this describes in M68KUM.

M68K user manual says !RESET (and !HALT) should be asserted at least 132 cycles to be safe, because the RESET instruction itself asserts !RESET during 124 cycles but that 10 cycles are enough to reset the processor if you don't care about RESET instruction (not sure how it behaves when the main ASIC is forcing reset line in high state and CPU drives it low).

Again, I agree it's not very important information but the point was more to document unverified stuff, for the "fun", you know.

I don't suppose you've looked at FRES?

I tried but couldn't really figure anything, even when !DISK input is forced to GND, I never saw it changing when !VRES and !ZRES are going low, only strange pulse (very short) that could as well be periodic noise. I tried picking up the signal directly at the connector or just before the resistor but it was the same. Maybe I'm doing something wrong, I really don't know as I didn't really spend much time on it then.

Eke wrote:I know it's logical, but I was playing with my new "toy" and it doesn't cost much time to confirm it

Personally I always think such research is necessary. Even if it's to confirm things already known, every bit of information is important. It's great that you are looking into these things.

I tried but couldn't really figure anything, even when !DISK input is forced to GND, I never saw it changing when !VRES and !ZRES are going low, only strange pulse (very short) that could as well be periodic noise. I tried picking up the signal directly at the connector or just before the resistor but it was the same. Maybe I'm doing something wrong, I really don't know as I didn't really spend much time on it then.

Hmm, that's okay then. Maybe it is only asserted in strange situations, like transitioning from CART pulled low to high. Sometime I'll try looking at it again.

I looked at the Mega CD schematics and it uses FRES, so at least we know it has some purpose.

So, has anyone played with FRES?
I've noticed pressing reset on MD doesn't reset gate array registers at all, actually even the bios on slave still seems to be active and I can communicate with it from a test program on cart.

FWIW, page 70 of 105 of the "Mega CD 1 of 2 A4.pdf" service manual has a description of the FRES signal in Japanese (renamed "IFRES"), as well as FDC ("IFDC") and other signals that go between the Mega Drive expansion port and 315-5548 inside the Mega CD.

Maybe somebody could translate the FRES description?

I couldn't see FRES changing when pushing the RESET button, i think it only reflects changes on SRES, which, as mentionned above, is asserted on Power On or when MRES input pin is asserted from cartridge.

From the early revisions schematics, you can see that FRES comes from the I/O chip, which only get SRES, not WRES/VRES

I've got someone to translate Japanese text as

When G/A is powered on and reset, the input indicator is activated.

So I suppose this means it is power on reset signal.
Still strange it's marked as I/O in MD2 service manual and not just output.

I did some tests on a Genesis 2 (VA0) today. FRES is pulsed high when you apply power, and otherwise always remains low.

The pulse width is about 137.4 ms wide. The falling edge is synchronous with the rising edge of SRES, e.g. 12.8ms before VRES# goes high, FRES goes low and SRES# goes high.

The rising edge is a little more complex. For some reason VRES# has a 2ms high pulse after the 7805 output has risen to about 4V, and the rising edge of FRES is synchronous with the falling edge of that short pulse. I'm fairly certain an original model Genesis did not do this on VRES#, so I can't say how FRES acts on that system.

Regardless, FRES appears to be an active-high reset signal triggered once during power-up and never again.