SpritesMind.Net

Code: Select all

SAR1 = source address (in ROM, SH2 address space)
DAR1 = mono pulse width register (0x20004038)
TCR1 = 1024 (some number long enough that I'd notice the output)
CHCHR1 = 0x14E1 (fits Sega's 00XX 0100 1110 0XXX recommended pattern for 16-bit transfers)
DRCR1 = 0
DMACR = 1

Wait... repeat.

Code: Select all

    // init the sound hardware
    MARS_PWM_CTRL = 0x0185; // TM = 1, RTP, RMD = right, LMD = left
    if (MARS_VDP_DISPMODE & MARS_PAL_FORMAT)
        MARS_PWM_CYCLE = 521; //44.1kHz
    else
        MARS_PWM_CYCLE = 516; //44.1kHz

    while (1)
    {
        // only do sound when sound subsytem initialized
        while (MARS_SYS_COMM4 == 1)
        {
            // start DMA on first buffer and fill second
            SH2_DMA_SAR1 = (unsigned long)sndbuf & 0x1FFFFFFF;
            SH2_DMA_DAR1 = (unsigned long)&MARS_PWM_LEFT & 0x1FFFFFFF; // storing a long here will set left and right
            SH2_DMA_TCR1 = (unsigned long)NUM_SAMPS; // number longs
            SH2_DMA_CHCR1 = (unsigned long)0x18E1; // dest fixed, src incr, size long, ext req, dack mem to dev, dack hi, dack edge, dreq rising edge, cycle-steal, dual addr, intr disabled, clear TE, dma enabled
            SH2_DMA_DMAOR = (unsigned long)1; // enable DMA - starts dma

            FillSoundBuff(NUM_SAMPS * 2 * 2);

            // wait on DMA
            while (!(SH2_DMA_CHCR1 & 2)) ; // wait on TE
            SH2_DMA_DMAOR = (unsigned long)0; // disable DMA
            SH2_DMA_CHCR1 = (unsigned long)0x18E0; // clear TE, dma disabled

            // start DMA on second buffer and fill first
            SH2_DMA_SAR1 = ((unsigned long)sndbuf & 0x1FFFFFFF) + NUM_SAMPS * 2 * 2;
            SH2_DMA_DAR1 = (unsigned long)&MARS_PWM_LEFT & 0x1FFFFFFF; // storing a long here will set left and right
            SH2_DMA_TCR1 = (unsigned long)NUM_SAMPS; // number longs
            SH2_DMA_CHCR1 = (unsigned long)0x18E1; // dest fixed, src incr, size long, ext req, dack mem to dev, dack hi, dack edge, dreq rising edge, cycle-steal, dual addr, intr disabled, clear TE, dma enabled
            SH2_DMA_DMAOR = (unsigned long)1; // enable DMA - starts dma

            FillSoundBuff(0);

            // wait on DMA
            while (!(SH2_DMA_CHCR1 & 2)) ; // wait on TE
            SH2_DMA_DMAOR = (unsigned long)0; // disable DMA
            SH2_DMA_CHCR1 = (unsigned long)0x18E0; // clear TE, dma disabled
        }
    }

Code: Select all

- write zero (3 words) to MONO (clear both FIFO)
- set PWM cycle register = 0x0209 (~ 44100 KHz)
- set PWM control register = 0x0185 (TM = 1; RTP = 1; Normal Stereo out)
- set DMA.SAR1 = 0x06020000 (RAM source)
- set DMA.DAR1 = 0x20004034 (FIFO dest : L+R)
- set DMA.TCR1 = 0x00002C00 (length is 44 KB)
- set DMA.CHCR1 = 0x00000000 (this clears the DE bit, just in case)
- set DMA.CHCR1 = 0x000018E1 (as expected)
- set DMA.DMAOR = 0x00000001 (go go gadget DMAC)