Sik wrote:I love how accurate emulators are, I tested five of them and there was no match between them in the output at all o_O So bad I can't test on the real hardware, but I would want to see a more zoomed version of the samples, I want to make sure it isn't just that the program skips the samples between pixels and gives inaccurate waveforms hence (this happens more often than you may think).
Of course the difference isn't only du to pixel alignment of waveform, when you listen sample on emulator then on real hardware it's *very* noticeable !
Usually, M-cycle is 4 clocks length and memory R/W-cycle is 3 clocks (of course with 0 wait states). So, 1 byte move opcode with REG-REG will 4 clocks and REG-(HL) - 7 clocks. So, most length of opcodes you can compute by its effects step by step. Don't forget: preffix are always 4 clocks (its M-cycle before opcode - another M-cycle).
For example, RET opcode: M-cycle C9h, memory read ADRL from stack, memory read ADRH from stack. So, 4+3+3=10 clocks (with 0 wait states).
Thanks HardwareMan for yours explanations, i guess i'll have to recalculate entirely all my routine cycles :p
So the "z80-documented.pdf" document was correct about T States infos.
The only thing I can think of is the response time of the YM chip for the DAC write. I've read that two fast of writes to the DAC will be ignored. Some external chips have a way of slightly delaying a processor when it writes to a port (not sure of the 68k has something similar to /RDY). It's possible that on the higher frequency writes, you're getting "misses" on misaligned writes. Dunno. Try doing a two sample square wave(a series of FF and 00) at higher frequencies and see what it looks like.
In fact i'm writing to the YM2612 port 18000 times per second which is "theorically" far from his limit (~55000 times per second). There is a busy flag on YM2612 but i don't waste time to read it as i don't have enough free time for that. Your square sample is a good idea, nice way to see how the DAC got it.
The sample rate being lower issue is because the Z80 accesses ROM when 68K isn't and Z80 has no priority for accessing ROM... but for distortion, I'll hear it...
I'll test the ROM ASAP and tell you my results and ideas.
EDIT : That distortion is caused by one thing called leakage, value written to DAC will go silence in a short period of time... on emulator it doesn't happen that's why speech sounds better... on real HW instrument like cymbals sound a bit better because of this.
Yep i though about the 68000 BUS being sometime busy can distorde sound but not in that range ! Futhermore it looks like some particular frequencies are more impacted than others.
About your silent period after a write to the DAC, do you have more information about it ? If it's really the reason of the poor quality... weird, i'm feeling really disapointed. I always though the bad speech quality in genesis games were only due to the Z80 interruption at each frame for DMA stuff and controllers read, but it is not !
EDIT: BTW, Regen runs it at 17900 Hz which is pretty close.
When only 1 sample is played hardware is close to 17900 Hz, the more channel are played, the lower the rate is because of more wait state on 68000 BUS access. You can also notice a FPS drop (which mean the 68000 is slowed down by the multiples Z80 BUS steals).
Tested on a NTSC genesis :
No sample = 788 FPS
1 sample = 767 FPS
2 samples = 754 FPS
no tested more as my demo doesn't permit it :p
On a PAL system the FPS stays to 0 because of a bug in my library.