I try to understand the order of bus transaction in MOVE memory,(xxx).L.
According to https://pasti.fxatari.com/68kdocs/68kPrefetch.html :
When the destination addressing mode is long absolute and the source operand is any memory addr.mode, step 4 is interleaved in the middle of step 3. Step 3 only performs a single prefetch in this case.
The other prefetch cycle that is normally performed at that step is deferred after the write cycles.
So, two prefetch cycles are performed after the write ones. It is a class 2 instruction. Note: The behavior is the same disregarding transfer size (byte, word or long). But if the source operand is a data or address register, or immediate, then the behavior is the same as other MOVE variants (class 1 instruction).
In Tom Harte Test Suit we have :
"name": "006 MOVE.b (d8, A6, Xn), (xxx).l 13f6",
"initial": {
"d0": 3231024118,
"d1": 763310398,
"d2": 2299392720,
"d3": 4196998473,
"d4": 3643198880,
"d5": 2970016506,
"d6": 2785099946,
"d7": 982711915,
"a0": 102178095,
"a1": 3073357110,
"a2": 2999152133,
"a3": 4234013280,
"a4": 813304631,
"a5": 2259847125,
"a6": 885874839,
"usp": 13458896,
"ssp": 7412874,
"sr": 8193,
"pc": 6853188,
"prefetch": [
5110,
33663
],
"ram": [
[ 6853184, 19 ],
[ 6853185, 246 ],
[ 6853186, 131 ],
[ 6853187, 127 ],
[ 6853188, 171 ],
[ 6853189, 215 ],
[ 13467204, 209 ],
[ 13467205, 135 ],
[ 6853190, 111 ],
[ 6853191, 79 ],
[ 6853192, 209 ],
[ 6853193, 146 ],
[ 6853194, 211 ],
[ 6853195, 4 ]
]
},
"final": {
"d0": 3231024118,
"d1": 763310398,
"d2": 2299392720,
"d3": 4196998473,
"d4": 3643198880,
"d5": 2970016506,
"d6": 2785099946,
"d7": 982711915,
"a0": 102178095,
"a1": 3073357110,
"a2": 2999152133,
"a3": 4234013280,
"a4": 813304631,
"a5": 2259847125,
"a6": 885874839,
"usp": 13458896,
"ssp": 7412874,
"sr": 8200,
"pc": 6853196,
"prefetch": [ 53650, 54020 ],
"ram": [
[ 6853184, 19 ],
[ 6853185, 246 ],
[ 6853186, 131 ],
[ 6853187, 127 ],
[ 6853188, 171 ],
[ 6853189, 215 ],
[ 13467204, 209 ],
[ 13467205, 135 ],
[ 6853190, 111 ],
[ 6853191, 79 ],
[ 14118734, 0 ],
[ 14118735, 135 ],
[ 6853192, 209 ],
[ 6853193, 146 ],
[ 6853194, 211 ],
[ 6853195, 4 ]
]
},
"transactions":[
["n",2],["r",4,6,6853188,".w",43991,1,1],
["r",4,5,13467204,".b",135,0,1],
["r",4,6,6853190,".w",28495,1,1],
["w",4,5,14118734,".b",135,0,1],
["r",4,6,6853192,".w",53650,1,1],
["r",4,6,6853194,".w",54020,1,1]],
"length":26
},
I don't understand the transaction order in the test :
["r",4,6,6853190,".w",28495,1,1],
["w",4,5,14118734,".b",135,0,1],
["r",4,6,6853192,".w",53650,1,1],
This is like M68000 write to destination address before reading his second word ! How is possible?
MOVE memory,(xxx).L Bus Transactions
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