SpritesMind.Net

DMA. I don't know a lot about it yet because I haven't coded up anything on the scale where i'd actually need it. But I was doing something and got to thinking about it. I know some of you guys would know.

Here's my questions:

1. How fast is the DMA to VDP RAM in tiles per frame?. Assuming 60hz vblank period. Is it fast enough to get a whole 320x224 screen's worth of tiles over (assume worst case!), or is that unrealistic?

2. Can the DMA function with out of 68K RAM -> VDP RAM copy?

3. As far as I know DMA takes the 68k off the bus till complete so with an operation of this magnitude how many cycles is it going to steal from the 68k?

http://www.tmeeco.eu/BitShit/VDPRATES.TXT

It is faster than 68K alone, and it will not be fast enough to transfer a screenful in one frame. 60Hz is also much slower than 50Hz.

Thanks Tiido. I didn't know someone would have a doc ready but if it would be anyone, it'd be you

Your numbers for 68K -> VRAM are off. The DMA engine can only do 198 68K reads per line, but those reads are word wide and VRAM is only byte wide so the bottleneck is on the write side. 68K -> VRAM transfers go through the FIFO so the read hiccup is not an issue. It's only for 68K -> CRAM and 68K -> VSRAM writes that the refresh cycles on the 68K side matter.

Also, there are 225 "active" lines even though only 224 are drawn. This is because sprite rendering occurs a line early and so it needs to process an extra line so that sprites can be drawn on the first line. In theory, the VDP could free up a bunch of external access slots in this extra line since the reads for drawing the background planes are not needed, but it's not smart enough to do this. The extra line does start a few slots late so you do get 4 extra writes on that line. My recollection is that you lose those at the end of the active period, but I'd have to check my logic analyzer captures to be sure.

So for H40 mode in 60Hz regions I get 4050 bytes during the active display period and 7548 bytes during the passive lines for a total of 11598 bytes. Not a huge difference since the extra active line mostly cancels out the extra 6 bytes per passive line. I suppose it might matter once you start disabling the display early to free up more bandwidth though.

powerofrecall wrote:2. Can the DMA function with out of 68K RAM -> VDP RAM copy?

I'm not sure what you mean exactly. VRAM copy and VRAM fill don't use the 68K's bus if that's what you're getting at. Unfortunately, VRAM copy has half the throughput of 68K->VRAM and VRAM fill is pretty limited.

powerofrecall wrote:3. As far as I know DMA takes the 68k off the bus till complete so with an operation of this magnitude how many cycles is it going to steal from the 68k?

The 68K is frozen until all the bytes to be transferred are in the FIFO. Since the FIFO can only store 4 words this is usually pretty close to the time for the full DMA except for small transfers during the active display period. There are 3420 master clock ticks per line and the 68K is running off of MCLK/7 so each line that the 68K is blocked costs you ~488.6 68K cycles. During the passive display period that means you lose ~2.39 cycles for every byte transferred (though this doesn't take into account the difference between all bytes in the FIFO and the DMA actually being complete).

Mask of Destiny wrote: I'm not sure what you mean exactly.

I think I can word it better: can the DMA source pointer be main RAM? Can you DMA RAM -> VRAM?

Thanks for the cycle info, I always wondered what the impact of it was.

^ good into there MoD ! I will have to update my docs sometime, I looked that it is pretttty old haha.
I have seen the extra active line myself when doing the VRAM visualisation.
The numbers are still a good reference to go by, and you cannot really achieve exact figures anyway in a typical game setting.

powerofrecall wrote:

Mask of Destiny wrote: I'm not sure what you mean exactly.

I think I can word it better: can the DMA source pointer be main RAM? Can you DMA RAM -> VRAM?

Of course! In fact, many games have the rom tile data compressed, so they decompress the rom into work ram, then DMA the work ram into vram. You can also DMA from CD word ram into vram, but there's a one word latency, so you have to either start one word early and go one word longer, or copy the first word using the CPU after the DMA is done.

I'd happy to write some Tutorials and give some Code as this was an issue that I had a couple of Weeks back.

The question: where to put the Tutorials? I can short list MD Wiki Squee that Tristan runs anywhere else?