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Re: Untitled 32X Super Scalar Project
Posted: Sat Jan 29, 2022 4:40 pm
by pw_32x
I'm not sure I'm doing this correctly. Flushing arrays properly has got me stumped.
Code: Select all
// main cpu
ClearArea* currentClearArea; // an array of areas to clear
ClearArea* clearAreaEnd = currentClearArea + clearAreasCount; // the end of the array
// on the second cpu
FlushMemory(currentClearArea, clearAreaEnd );
And FlushMemory looks like
Code: Select all
void FlushMemory(void* start, void* end)
{
// does it have to be aligned on 16 bytes?
u8* runner = (u8*)start; //(u8*)(((u32)start >> 4) << 4);
while (runner < (u8*)end)
{
u8* flushRunner = (u8*)((u32)runner | 0x60000000);
*flushRunner = 2; // write anything?
runner += 16; // skip to the next 16 bytes
}
}
The FlushMemory call above isn't quite what I'm using. I'm actually calling
Code: Select all
FlushMemory((ClearArea*)UNCACHE_PTR(currentClearAreas), clearAreaEnd);
to make things work, which I don't quite get. Uncaching clearAreaEnd breaks things as well as using the cached version of currentClearAreas.
Re: Untitled 32X Super Scalar Project
Posted: Sat Jan 29, 2022 11:53 pm
by pw_32x
I've been experimenting a bit more. I've also been trying to reproduce a cache inconsistency between both cpus just so I can experiment with uncaching and flushing and I just haven't been able to. Oh delicious irony.
Re: Untitled 32X Super Scalar Project
Posted: Sun Jan 30, 2022 5:16 pm
by Chilly Willy
Whoops! Big whoospi on my behalf... it's 0x40000000, not 0x60000000. Sorry about that. Don't know how I confused the two.
In case you are wondering and don't want to actually go read the SH2 hardware manual...
0x00000000 = cached access
0x20000000 = uncached access (they call it cache-through, unlike how most other companies refer to it)
0x40000000 = associative purge access (cache line flush)
0x60000000 = access cache address array
0xC0000000 = access cache data array (scratchpad mode - no scratch + 4K cache, 2K scratch + 2K cache, or 4K scratch + no cache)
0xE0000000 = internal access (I/O blocks inside mpu)
8 and A are not defined in the manual.
Re: Untitled 32X Super Scalar Project
Posted: Sun Jan 30, 2022 5:56 pm
by pw_32x
Chilly Willy wrote: Sun Jan 30, 2022 5:16 pm
Whoops! Big whoospi on my behalf... it's 0x40000000, not 0x60000000. Sorry about that. Don't know how I confused the two.
Aha!
No worries!
In case you are wondering and don't want to actually go read the SH2 hardware manual...
I actually tried but I find it sometimes difficult to interpret the low-level hardware terminology.
"Associative purge space"... uhhh, sure.
Re: Untitled 32X Super Scalar Project
Posted: Mon Jan 31, 2022 12:14 am
by Chilly Willy
pw_32x wrote: Sun Jan 30, 2022 5:56 pm
I actually tried but I find it sometimes difficult to interpret the low-level hardware terminology.
"Associative purge space"... uhhh, sure.
The SH2 has three cache modes: no cache at all (all the cache data array being used as 4KB of fast scratch ram), 2KB two-way set associative cache + 2KB scratch ram, and 4KB four-way set associative cache + no scratch ram. The cache address array is where the association between the physical address of a line and it's place in the cache data array is kept. So flushing the cache is purging the associative information from the cache address array (it simply clears the valid bit for the line). Generally, you cannot directly access this information on most processors. It's kinda funny that the SuperH allows this. You could make your own cache line clear function by reading the appropriate part of the cache address array, modify the bits, and write it back. I think it's only meant for really low-level testing.
The SuperH was an interesting processor. At a time when fast cpus with "large" caches would run you several hundred dollars, the SH1/2/3/4 stood out as providing high speed and large caches at a bargain price. Hell, you could afford to put TWO in a device that sold for $150-ish! I'm a little saddened that no home computers used it.