Combinatorial/Sequential divider?

[Jorge Nuno]

Besides the subtracting/comparing n.times and the count/multiplying/comparing is there any method to do A/B for any given A and B?

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[tomaitheous]

Besides the subtracting/comparing n.times and the count/multiplying/comparing is there any method to do A/B for any given A and B?

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An example of binary division.

Code: Select all

    1100   remainder 1 
    ------
101/111101          
   -101 
    ------
     10101 
    -101
    ------- 
        01 

Taken from the WDC progamming manual:

There are several methods for doing this, but all are based on the division principles for multi-digit
numbers that you learned in grade school. Line up the divisor under the left-most set of digits of the dividend,
appending an imaginary set of zeroes out to the right, and subtract as many times as possible. Record the
number of successful subtractions; then shift the divisor right one place and continue until the divisor is flush
right with the dividend, and no more subtractions are possible. Any non-subtractable value remaining is called
the remainder.

Not sure if that's what you're looking for. It's a shift/subtract method (faster than the subtract/count/compare way of doing it).

Here's a link of some source in 65816 code for the logic (short listing) - here.

[Jorge Nuno]

Its to implement in a FPGA, so gates aren't a problem, but the number of stages is, because the more stages it takes the faster the master clock has to be...

I want to do this so I could have a faster divider/multiplier for the MD 68000.


It is to be something like (for 32bit division of d0/d1):
MOVE.l d0, $3FFFF8 ;d0: DDDDDDDD
MOVE.l d1, $3FFFFC ;d1: dddddddd
MOVE.l $3FFFF8, d2 ;d2: QQQQQQQQ
MOVE.l $3FFFFC, d3 ;d3: RRRRRRRR

D=Q*d+R

The multiplier is finished, and it's mapped in $3FFFF0 now

This address can be changed to anything in the 68k space but 3FFFFX seems to be empty in every 4MB game I have...