mcd-verificator (CD core accuracy tests)

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Eke
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Re: mcd-verificator (CD core accuracy tests)

Post by Eke » Tue Jul 21, 2020 10:48 am

I don't think the problem with MCD emulation on flashcarts with 32x is caused by /DTACK since /DTACK is asserted by the console itself when accessing Mega CD registers (in 0xA120xx range). I believe the problem is due to 32X not connecting all address lines to cartridge, which makes it impossible to decode Mega CD registers accesses from the flashcart.

Chilly Willy
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Re: mcd-verificator (CD core accuracy tests)

Post by Chilly Willy » Tue Jul 21, 2020 4:47 pm

A23-A22/A18-A1 from the Genesis are all connected through to the cart. A21-A19 are fed from the IO chip. When the 32X is disabled, or when it's enabled and the RV bit is set, those lines should be passed through from A21-A19 from the Genesis. When the 32X is enabled and RV=0, A21-A19 come from a combination of the bank select bits inside the IO chip and the address, allowing the 32X to present two places where the 68K can read the cart rom. Since carts can be up to 4MB directly addressed, and since that requires lines up to A21, the 32X MUST be passing through A21-A19 unchanged when disabled or RV=1. So I don't see any reason related to the address lines that the 68K cannot read the CD range on a cart plugged into the 32X, as long as the 32X is disabled or RV=1.

EDIT: Actually, while showing A23-A22 from the Genesis connected to the mux, it's possible that those two lines aren't really connected. If that was the case, then you couldn't access the CD through the 32X. Someone would need to check their 32X - test from the 32X edge to the lines on IC5 (the address mux in the 32X). Pin 6 should be connected to VA23, and pin 7 to VA22.

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Re: mcd-verificator (CD core accuracy tests)

Post by Miquel » Fri Jul 24, 2020 8:54 pm

If signals like, for example, !TIME have a definitive impact in the address decoding of the MCD, I think they should be considered part of the address lines.
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Re: mcd-verificator (CD core accuracy tests)

Post by KRIKzz » Mon Jul 27, 2020 4:06 pm

I made some tests with 32x and is seems like 32x does not pass data lines in memory areas related to mega cd, may be it been made to avoid bus conflicts.

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Re: mcd-verificator (CD core accuracy tests)

Post by Chilly Willy » Tue Jul 28, 2020 12:22 am

KRIKzz wrote:
Mon Jul 27, 2020 4:06 pm
I made some tests with 32x and is seems like 32x does not pass data lines in memory areas related to mega cd, may be it been made to avoid bus conflicts.
Makes sense - the IO chip can decode the CD space and tri-state the data bus to make sure an attached CD doesn't have an extra load on the bus to work against. No telling how strong (or weak) the CD bus drivers are. The 32X had some issues in general with the CD, so it doesn't surprise me. One thing that had been planned with the 32X was a mode for the 68K to SH2 DMA where the FIFO was triggered any time the MD VDP did DMA from the CD word ram space. That way you could in effect DMA from CD word RAM to the SH2 DMA into SDRAM, making very fast CD to 32X data transfers without any processor overhead. They couldn't get it to work, so the official release has the bit that activates it set as forced to off, and mention of it in the manual removed. The 68K to SH2 FIFO is flakey as it is - even when using the 68000 to set the FIFO, it can lose data. Most games (that use it, many don't) use small packets, checksum the data, and use timeouts to tell when data is lost or corrupted. It's why that SuperVDP demo for the 32X released some time back doesn't work on real hardware - the author had no idea the 68K to SH2 FIFO DMA was flakey.

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Re: mcd-verificator (CD core accuracy tests)

Post by KRIKzz » Tue Jul 28, 2020 1:14 am

I just done small hack for remapping mcd registers area 0xA120XX and now i can run mcd via 32x. Seems it works fine, so now we know for sure that it is the only reason why mcd does not work via 32x

Miquel
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Re: mcd-verificator (CD core accuracy tests)

Post by Miquel » Tue Jul 28, 2020 5:09 am

If registers are only accessed from the BIOS that solves the problem.

@Chilly Willy are you saying that MCD doesn’t put the 68K bus in high impedance when hasn't taken the MD-68K bus?
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Re: mcd-verificator (CD core accuracy tests)

Post by neodev » Tue Jul 28, 2020 5:58 am

Also, maybe I'm wrong, as it has been a long time since I last looked into it for megasd, but the data write to cd registers could be seen briefly when the write signal is released, at least in my 32x unit. But there was no workround for reads.

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Re: mcd-verificator (CD core accuracy tests)

Post by Chilly Willy » Tue Jul 28, 2020 10:11 pm

Miquel wrote:
Tue Jul 28, 2020 5:09 am
@Chilly Willy are you saying that MCD doesn’t put the 68K bus in high impedance when hasn't taken the MD-68K bus?
No, I was saying the 32X puts the 68K bus in high impedance to avoid loading down the CD. When the MD 68K tries to access the registers, the CD is supposed to respond. If the 32X didn't tri-state the bus, there's another load on the bus besides the CD ASIC that the ASIC must then deal with when driving the bus to respond to the MD 68K.

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Re: mcd-verificator (CD core accuracy tests)

Post by Muzzy » Sun Sep 13, 2020 7:01 pm

So, with all that research work being done, - it is possible to read CD-text information from audio CD? Or maybe I'm not aware, and there is already done replacement for stock MegaCDplayer with that functionality?

Mask of Destiny
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Re: mcd-verificator (CD core accuracy tests)

Post by Mask of Destiny » Sat Jan 22, 2022 4:15 am

KRIKzz wrote:
Tue Jul 14, 2020 9:26 pm
Eke wrote:
Tue Jul 14, 2020 4:50 pm
This seems to indicate there are actually 32 registers in CDC chip, not 16 as described in LC591x manual, and that AR register (register index) does not reset to 0x00 when register 0xF is read but when register 0x1F is read, which again contradicts LC591x manual and is kinda unexpected.

Did you confirm this on all Mega CD models?
Do you know what is returned when reading these registers ?

PS: I don't think bit 4 is related to RS signal, as this signal is specifically used to tell the chip to update the AR register value when writing to the chip with RS=0. Even if this bit was used to force the value of RS signal, it would not explain why it would suddenly be set after accessing register 0xF.
I tested it with cdx and mcd2. From what i can remember RS+AR pair acts as internal 5-bit address register, with RS as most significant bit. RS=0 means that you access to regs 0-15, RS=1 for regs 16-31. Regs 16-31 have no any effect and returns 0xff if read them. Gate array reg 0x8005 also actually show 5bit value.
Finally getting around to implementing Mega CD support in BlastEm and all the hardware I have on hand fails CDC register test 01. I tested with a Wondermega M1, Sega CD 2 (Sony) and a Laseractive with Sega PAC S-10. The Wondermega and Sega CD2 also fail CDC FLAGS test 40 with a value of 25 (I can't test on the Laseractive at the moment as the drive mechanism needs repair). My Sega PAC has an LC8951 (I believe that's also the case for the Wondermega M1 based on info I've seen online, but I didn't crack mine open to check) and the Sega CD2 has an LC89515. It seems like the CDX has an LC8913 though for which we seem to only have a very basic datasheet. Perhaps that chip (and perhaps the LC8913K used in the Wondermega M2/JVC X'Eye) are the only ones that exhibit this 5-bit AR behavior? Doesn't explain how this test works on your MCD2 though.

Thanks so much for the tests though! Been a big help so far.

Eke
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Re: mcd-verificator (CD core accuracy tests)

Post by Eke » Sun Feb 27, 2022 9:07 am

Another particularity I recently noticed is that the X'Eye (and likely Wondermega M2) was using 32KB RAM chip (LC33832) with the CDC (LC89513) instead of 16KB in all other Mega-CD models.

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