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Concurrency penalty

Posted: Sun May 16, 2021 4:36 pm
by ob1
Hello to you all.
Working on a personnal project, I was able to benchmark the penalty of the Master / Slave concurrency Bus Access.
As you know, when Master and Slave both want to access the bus, the Master has the priority, and the Slave can access the bus when it receives the permission to do it.
My test code was:

Code: Select all

!loop:
	MOV.W	R12,@R1    ; Write to DRAM
	ADD	#1,R9
	CMP/HI	R9,R13
	BF/S	!rarely
	ADD	#2,R1
	DT	R11
	BF/S	!loop
	MOV.W	@R10+,R12    ; Read from SDRAM
Running this same slice of code on both Master and Slave gave me this result:
concurrency between Master and Slave makes the Slave between 6 an 10% slower.
Your mileage may vary.
Tested on real PAL hardware.

I thought this could help ^^

Re: Concurrency penalty

Posted: Sun May 16, 2021 9:39 pm
by Chilly Willy
I like these in-depth analyses you're doing on the 32X. Makes some oddities about the hardware easier to understand, and maybe deal with.

Re: Concurrency penalty

Posted: Fri May 21, 2021 4:47 pm
by djcouchycouch
WIth my 32x experiments, these are definitely related to my interests! It's great!

Re: Concurrency penalty

Posted: Fri May 21, 2021 8:21 pm
by ob1
Glad it helps ^^