Questions on emulating the 32X
Posted: Mon Mar 22, 2021 11:32 am
Hi all, I started on a 32X emulator. It's far enough to run Chaotix, but not much else.
Problem is, it's feature-complete. I implemented the VDP, PWM, FIFOs, DREQ, vector 4 address (0x70-0x73) as RAM, and the half of the SH7804 games use: full cache emulation (including all CCR bits, the LRU, address read/write, purge, write-through, etc), 32-bit and 64-bit division (with the division register mirroring Virtua Fighter relies on and IRQs on overflow), DREQ DMAs (all sizes and address increment modes supported) and completed IRQs, 16-bit timer support along with frequency scalar and IRQ support, master<>slave SCI communication and transmit/receive IRQ support, and then for everything else I implemented reading and writing the internal SH7604 registers, but not the actual functionality yet (no way to test it if no games use it, and some of it would be very costly to do just for fun.
Throwing my questions / issues out there in the hopes someone recognizes one ^-^;
1. I fail the Mars Test HINT (2) tests. The manual says an HCOUNT of 0 means every line, but from the Mars Test, I assume an HCOUNT of 1 is equal to 0 as every single line? Mars Test sets a value of 5, and reports "actual: 0000" if I take it to mean 6, or "actual: 061e" if I take it to mean 5. The expected value seems to be ~0x4d0 - 0x520, which implies to me something is running too fast. But no matter how much I slow down the SH2s, the result doesn't change. I don't believe my 68K/VDP emulation timing is that far off. I do emulate the "HINTs during VINTs" part. Removing that (which is wrong, the bit is set) drops it to "actual: 0540" which still fails.
2. I fail the Mars Test SH2 DMA tests (#121 and 122.) They are expecting 68S to get set to zero when the length decrements to zero. It sets length to 0x800. If I clear 68S after 0x800 (writes to the FIFO register from the 68K -or- reads from the FIFO register from one of the SH2s), then the test hangs forever. If I don't clear 68S, then the tests fail expecting it to have been cleared. Mars Test #123 locks up. I know the test overwrites program memory, but my cache emulation is complete, so I suspect it's related to failing #121/122.
3. Virtua Fighter shows no polygons when you start a fight.
4. Virtua Racing Deluxe shows no graphics after the SEGA splash screen, but I can hear the music, and the game is playing.
5. Doom shows no in-game graphics, just a brown screen. The rest of the HUD all renders correctly.
6. I have to do the frame buffer swapping immediately, or lots of graphics render incorrectly. Whether I report the true framebuffer or delayed framebuffer state when reading the VDP status register, games break badly if I delay the frame buffer swapping until Vblank. I am reporting the Vblank status in the VDP status register.
7. I don't really understand DREQ DMA. What does the DMA bit (d1) do exactly? It states it's for ROM to VRAM, but do we need to do anything beyond disable SH2 access to the ROM during this time? I presume the 68K DMAs from ROM to the FIFO register in this mode. How would the 16-byte DMA transfer size work? The FIFO only holds 2x4 words, we'd need twice that or it'll run out halfway through.
Problem is, it's feature-complete. I implemented the VDP, PWM, FIFOs, DREQ, vector 4 address (0x70-0x73) as RAM, and the half of the SH7804 games use: full cache emulation (including all CCR bits, the LRU, address read/write, purge, write-through, etc), 32-bit and 64-bit division (with the division register mirroring Virtua Fighter relies on and IRQs on overflow), DREQ DMAs (all sizes and address increment modes supported) and completed IRQs, 16-bit timer support along with frequency scalar and IRQ support, master<>slave SCI communication and transmit/receive IRQ support, and then for everything else I implemented reading and writing the internal SH7604 registers, but not the actual functionality yet (no way to test it if no games use it, and some of it would be very costly to do just for fun.
Throwing my questions / issues out there in the hopes someone recognizes one ^-^;
1. I fail the Mars Test HINT (2) tests. The manual says an HCOUNT of 0 means every line, but from the Mars Test, I assume an HCOUNT of 1 is equal to 0 as every single line? Mars Test sets a value of 5, and reports "actual: 0000" if I take it to mean 6, or "actual: 061e" if I take it to mean 5. The expected value seems to be ~0x4d0 - 0x520, which implies to me something is running too fast. But no matter how much I slow down the SH2s, the result doesn't change. I don't believe my 68K/VDP emulation timing is that far off. I do emulate the "HINTs during VINTs" part. Removing that (which is wrong, the bit is set) drops it to "actual: 0540" which still fails.
2. I fail the Mars Test SH2 DMA tests (#121 and 122.) They are expecting 68S to get set to zero when the length decrements to zero. It sets length to 0x800. If I clear 68S after 0x800 (writes to the FIFO register from the 68K -or- reads from the FIFO register from one of the SH2s), then the test hangs forever. If I don't clear 68S, then the tests fail expecting it to have been cleared. Mars Test #123 locks up. I know the test overwrites program memory, but my cache emulation is complete, so I suspect it's related to failing #121/122.
3. Virtua Fighter shows no polygons when you start a fight.
4. Virtua Racing Deluxe shows no graphics after the SEGA splash screen, but I can hear the music, and the game is playing.
5. Doom shows no in-game graphics, just a brown screen. The rest of the HUD all renders correctly.
6. I have to do the frame buffer swapping immediately, or lots of graphics render incorrectly. Whether I report the true framebuffer or delayed framebuffer state when reading the VDP status register, games break badly if I delay the frame buffer swapping until Vblank. I am reporting the Vblank status in the VDP status register.
7. I don't really understand DREQ DMA. What does the DMA bit (d1) do exactly? It states it's for ROM to VRAM, but do we need to do anything beyond disable SH2 access to the ROM during this time? I presume the 68K DMAs from ROM to the FIFO register in this mode. How would the 16-byte DMA transfer size work? The FIFO only holds 2x4 words, we'd need twice that or it'll run out halfway through.