cache access

[ob1]

Hi you all.
I've started developping on 32X (enough theory, let's get on practice), and I'm having some troubles with cache. Here's the deal.
By fetching an instruction, the cache should be filled. And, doing something like

Code: Select all

        mov        #1,R0
        mov.l      REG_CCR,R1
        mov.b      R0, @R1                ; Cache enable
        mov        RAM_START,R8
test:
        mov        @R8,R7                ; read SDRAM
        add        #1,R10                ; Check the CPU is actually running
        bra        test
        nop

REG_CCR:        dc.l        $FFFFFE92
RAM_START:      dc.l        $06000000

should fill the cache too. By looking at GensKMod 0.7, I can't see the cache changing.

Is cache implemented on Gens, or is it just private Work-RAM ? Is cache viewable in GensKMod, or is it just private Work-RAM either ?