Working on a personnal project, I was able to benchmark the penalty of the Master / Slave concurrency Bus Access.
As you know, when Master and Slave both want to access the bus, the Master has the priority, and the Slave can access the bus when it receives the permission to do it.
My test code was:
Code: Select all
!loop: MOV.W R12,@R1 ; Write to DRAM ADD #1,R9 CMP/HI R9,R13 BF/S !rarely ADD #2,R1 DT R11 BF/S !loop MOV.W @R10+,R12 ; Read from SDRAM
concurrency between Master and Slave makes the Slave between 6 an 10% slower.
Your mileage may vary.
Tested on real PAL hardware.
I thought this could help ^^