On the project I'm currently working on, I've noted that I had to wait some time between setting CPU WRITE ($A15107b.2) and the first transfer from 68k to DREQ FIFO.Chilly Willy wrote: ↑Wed Oct 31, 2012 1:21 amWhen doing 68K to 32X DMA via the FIFO in the 32X, it has a tendency to lose data randomly. Specifically, the DREQ fails to trigger the DMA under unknown circumstances, which means the SH2 DMA stops. If you are checking the FIFO full flags, it will "stick" at full because the DMA is no longer emptying the FIFO.
I'll try to find why it loses the DREQ, but it might be that this is something that will have to be worked around... a hardware bug not fixed before the production model chips were made.
11 NOPs seems to be the bare minimal, but I'm more at ease with ~100 cycles.
This delay might be needed for the DREQ circuitry to warm-up, or the SH2 to get all the needed infos.
Tested on Fusion 3.64 and GensKMod 073.