- DMA type is Copy to CRAM (or VSRAM), which means the DMA rate is 205 words per line (don't forget display is disabled which is equivalent as DMA during vblank !)
- DMA length is 16 words which mean 68k should be frozen during
16x(3420/7)/205 = 38 CPU cycles
There seems to be a problem with your DMA cycles calculation, it should not be that long (the display OFF/DMA trick is used for that reason) and should easily remains in the HBLANK period
(Also, be sure you are handling long writes correctly, upper word first)
well, according to the 68k user manual, Bus Access is granted between memory cycles so theorically, this could happen.I really doubt you can freeze the CPU in the middle of instruction. At least you can't interrupt it like this for sure. There is some delay between writing the command and actual DMA start/CPU freeze anyway
but you are right, VDP reaction is not immediate and the end of the next memory write cycle (end of instruction) would probably be executed before the VDP sends a Bus Request
It's also very likely that in this case, the VDP would also disable the display AFTER the DMA operation has been finished, so that the DMA operation benefits of higher transer capacity.
This is how it was originally coded for and the way you should emulate it I think.