Megadrive video timings

For anything related to VDP (plane, color, sprite, tiles)

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HardWareMan
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Re: Megadrive video timings

Post by HardWareMan » Sat Jan 28, 2017 8:26 am

Thank you!

mickagame
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Re:

Post by mickagame » Thu Mar 04, 2021 12:53 pm

Eke wrote:
Wed Feb 24, 2010 8:44 am
Since most emulators do the DMA immediately anyhow it's not really a concern. My emulator performs more like the real system in that the 68K is frozen and all other components run until the DMA is finished (with the appropriate slots). Since I am using Musashi I needed to handle the case where this happens as it ruins the game display otherwise and Musashi runs on instruction granularity, not cycle.
What I am doing is using a cycle count for 68k and a main cycle count for VDP events (line/frame). The main cycle count is incremented by 3420 cycles per line and, as long 68k current cycle count is above the wanted main cycle count, no cycles are executed but other chips (incl. VDP) keeps running.

So when DMA occurs, just add the exact number of cycles required by DMA to 68k cycle count and you are set. Afaik, no games rely on tight timings for the 'after DMA' 68k instruction occurence (i.e if it's a write that affect VDP, it always occurs in good time, for example during HBLANK), so you don't really need cycle granularity for 68k when it's "frozen" (only for VDP rendering) , as long as you properly "freeze" the CPU as soon as the writes that trigger DMA is done. Also keep in mind that VDP might have some latency when handling data/register writes from CPU and CPU bus request, so 68k cycle granularity won't give you necessarely more precision...
My emulator has a flickering display if I do the DMA due to the way I emulate the system mentioned above, there could be bugs in it but am just wondering if there is a knowledge gap here on DMA. If I skip the DMA the display is much closer to how other emulators display it.
Most game disable the display before doing DMA or do this in VBLANK/HBLANK, so you shouldn't notice any flickering. In other case, it's very unlikely the DMA is going to affect VDP RAM regions used for the current frame/line.
Also don't forget some VDP settings are latched during HBLANK, and especially Verticall Scroll RAM values that are sometime written by games DURING active line but shouldn't be taken in account until next one, I know a few games (Lotus 2 for example) that rely on this. I bet it is different when you enable 2-cell vertical scroll but those games don't use this and I'm pretty sure horizontal & vertical scroll offsets for each plane are fetched/calculated once before line rendering.
I was reading this interesting discussion from 2010 (Time flies !!!).
Eke if you read this post i don't see very good how you emulate DMA trigger in middle of instruction in genesis plus.
When 68k write the first word what happen in vdp code? You execute the vdp until the DMA finish (render all the line necessary) and then switch back to 68k core to execute second word write?

Eke
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Re: Megadrive video timings

Post by Eke » Fri Mar 05, 2021 9:15 am

Eke if you read this post i don't see very good how you emulate DMA trigger in middle of instruction in genesis plus.
When 68k write the first word what happen in vdp code? You execute the vdp until the DMA finish (render all the line necessary) and then switch back to 68k core to execute second word write?
The first word write starts the DMA operation (which will be processed on a line-by-line basis since emulator granularity is line-based) and forces the 68k cycle counter to DMA end cycle to simulate 68k CPU being locked from bus during DMA (68k core will not execute any more instructions until its cycle counter is inferior to system cycle counter).

The 2nd word write access is still done by the CPU but its has no effect on VDP (see https://github.com/ekeeke/Genesis-Plus- ... trl.c#L697) and will be processed when DMA is finished (see https://github.com/ekeeke/Genesis-Plus- ... trl.c#L677). Note that this is likely not what happen exactly on real hardware (the 2nd write is not 'buffered' by the VDP and is rather not done by CPU until DMA is finished and bus released) but musashi 68k core does not all allow halting the CPU in the middle of an instruction (between the two bus accesses) and it makes zero difference in the end. There is no 'switch' between cores as this emulator is not thread-based.

mickagame
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Re: Megadrive video timings

Post by mickagame » Fri Mar 05, 2021 9:28 am

Thanks for informations. All is clear now :-)

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