Megadrive video timings
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Megadrive video timings
Taken from a 53.2034MHz MD in NTSC mode running demos from S&K
Vsync, Hsync and Csync are forced low, but not high, only released, the pull-ups slowly drive them high, after a while, so EDclk is in "slow mode" (Mclk/5) for 3 cycles, because the 315-5433 looks at theese signals to produce the EDclk.
/Csync on Yellow;
/YS on Green;
/IPL2 on Purple;
EDclk (after FB7) on Blue (AC coupled, forgot to fix that, but it doesn't change anything at all)
9 lines have shorter hsync pulses and middle pulses of the same length.
A full Hsync pulse is forced low by the VDP N-mosfet and after 64 EDclks (7Mclks/4 + 57Mclks/5) it's released, but because it's not forced high (only pulled), EDclk is still Mclk/5 for 3 cycles while hsync is rising, then the 315-5433 toggles EDclk back to Mclk/4.
Half Hsync pulses are 32 EDclks (3Mclks/4 + 29Mclks/5), same history with the slowly rising edges.
Line 31 (in NTSC) is the first VDP-drawn line.
A close-up on line 254. The color borders are both 26EDclks(Mclk/4).
Errata: Nope, the back border is longer, it's 28EDclks.
The front-porch (hsync released to YS falling) is 64EDclks long (3Mclks/5 + 61Mclks/4)
The back-porch (YS rising to hsync falling) is 18EDclks long (18Mclks/4)
The blanking period is just a sum of everything above + sync period.
Vint is triggered in here. It's 40EDclks (3Mclks/5 + 37Mclks/4) after hsync is released.
The 262nd line, the last one in this pseudo NTSC.
PAL mode coming soon
Vsync, Hsync and Csync are forced low, but not high, only released, the pull-ups slowly drive them high, after a while, so EDclk is in "slow mode" (Mclk/5) for 3 cycles, because the 315-5433 looks at theese signals to produce the EDclk.
/Csync on Yellow;
/YS on Green;
/IPL2 on Purple;
EDclk (after FB7) on Blue (AC coupled, forgot to fix that, but it doesn't change anything at all)
9 lines have shorter hsync pulses and middle pulses of the same length.
A full Hsync pulse is forced low by the VDP N-mosfet and after 64 EDclks (7Mclks/4 + 57Mclks/5) it's released, but because it's not forced high (only pulled), EDclk is still Mclk/5 for 3 cycles while hsync is rising, then the 315-5433 toggles EDclk back to Mclk/4.
Half Hsync pulses are 32 EDclks (3Mclks/4 + 29Mclks/5), same history with the slowly rising edges.
Line 31 (in NTSC) is the first VDP-drawn line.
A close-up on line 254. The color borders are both 26EDclks(Mclk/4).
Errata: Nope, the back border is longer, it's 28EDclks.
The front-porch (hsync released to YS falling) is 64EDclks long (3Mclks/5 + 61Mclks/4)
The back-porch (YS rising to hsync falling) is 18EDclks long (18Mclks/4)
The blanking period is just a sum of everything above + sync period.
Vint is triggered in here. It's 40EDclks (3Mclks/5 + 37Mclks/4) after hsync is released.
The 262nd line, the last one in this pseudo NTSC.
PAL mode coming soon
Last edited by Jorge Nuno on Sat Feb 14, 2009 12:05 am, edited 1 time in total.
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thank you very much Jorge ...
some stuff that I still would like to know eventually:
1/ Hint triggering regarding to hsync : check IPL2 and IPL1 with a game using the horizontal interrupt
2/ does Vint remains pending and how long if not acknowledged by CPU: check IPL1 from line 224 with interrupts disabled on 68k, would require a test ROM
3/ same for Hint, check IPL2 with Vint disabled on the VDP and interrupts disabled on 68k, would require a test ROM
4/ measure IPL1/IPL2 when both Hint and Vint are set on line 224
5/ same measures in H32 mode only ... and in PAL mode
but thanks again, those are already very valuable informations to me
so, if I didn't make any mistake with calculations, this would mean, that in H40 mode:
- Hblank area is (86/2) + (60/2) = 73 "pixels" count (43 "H40" pixels and 30 "H32" pixels)
--> (43*8 + 30*10)/7 = 92 CPU cycles
- Overscan area is 2 x 13 = 26 "H40" pixels
--> 26*8/7 = approx. 30 CPU cycles
- Full line width is 320 + 73 + 26 = 419 pixels count (389 "H40" pixels and 30 "H32" pixels)
--> (389*8 + 30*10)/7 = 3412/7 = approx. 487.5 CPU cycles
Could you measure the two borders more precisely, It seems one is wider than the other (btw, in H32 mode, it is supposed to be 15 +13 pixels, maybe it's still the case here)
also, still according to Charles McDonald, Hcounter range is 00-B6;E4-FFh which is actually 421 or 422 dot counts, which would tends to confirm the border area is a little "wider"
some stuff that I still would like to know eventually:
1/ Hint triggering regarding to hsync : check IPL2 and IPL1 with a game using the horizontal interrupt
2/ does Vint remains pending and how long if not acknowledged by CPU: check IPL1 from line 224 with interrupts disabled on 68k, would require a test ROM
3/ same for Hint, check IPL2 with Vint disabled on the VDP and interrupts disabled on 68k, would require a test ROM
4/ measure IPL1/IPL2 when both Hint and Vint are set on line 224
5/ same measures in H32 mode only ... and in PAL mode
but thanks again, those are already very valuable informations to me
so, if I didn't make any mistake with calculations, this would mean, that in H40 mode:
- Hblank area is (86/2) + (60/2) = 73 "pixels" count (43 "H40" pixels and 30 "H32" pixels)
--> (43*8 + 30*10)/7 = 92 CPU cycles
- Overscan area is 2 x 13 = 26 "H40" pixels
--> 26*8/7 = approx. 30 CPU cycles
- Full line width is 320 + 73 + 26 = 419 pixels count (389 "H40" pixels and 30 "H32" pixels)
--> (389*8 + 30*10)/7 = 3412/7 = approx. 487.5 CPU cycles
Could you measure the two borders more precisely, It seems one is wider than the other (btw, in H32 mode, it is supposed to be 15 +13 pixels, maybe it's still the case here)
also, still according to Charles McDonald, Hcounter range is 00-B6;E4-FFh which is actually 421 or 422 dot counts, which would tends to confirm the border area is a little "wider"
Last edited by Eke on Fri Feb 13, 2009 2:40 pm, edited 4 times in total.
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thanks,
so, again:
- Hblank area is (86/2) + (60/2) = 73 "pixels" count (43 "H40" pixels and 30 "H32" pixels)
--> (43*8 + 30*10)/7 = 92 CPU cycles (644 Mcycles)
- Overscan area is 14 +13 = 27 "H40" pixels
--> 27*8/7 = approx. 31 CPU cycles (216 Mcycles)
- Full line width is 320 + 73 + 27 = 420 pixels count (390 "H40" pixels and 30 "H32" pixels)
--> (390*8 + 30*10)/7 = 3420/7 = approx. 488.5 CPU cycles
This also means a "line" is 3420 Mcycles, active width being 2560 Mcycles and blanking being 860 cycles, which is similar to Charles's tests in SMS mode (framerate is 53693175/3420/262 = 59.92 fps in both modes) and values in 32x documentation (as posted here)
I love when everything starts to fit correctly
so, again:
- Hblank area is (86/2) + (60/2) = 73 "pixels" count (43 "H40" pixels and 30 "H32" pixels)
--> (43*8 + 30*10)/7 = 92 CPU cycles (644 Mcycles)
- Overscan area is 14 +13 = 27 "H40" pixels
--> 27*8/7 = approx. 31 CPU cycles (216 Mcycles)
- Full line width is 320 + 73 + 27 = 420 pixels count (390 "H40" pixels and 30 "H32" pixels)
--> (390*8 + 30*10)/7 = 3420/7 = approx. 488.5 CPU cycles
This also means a "line" is 3420 Mcycles, active width being 2560 Mcycles and blanking being 860 cycles, which is similar to Charles's tests in SMS mode (framerate is 53693175/3420/262 = 59.92 fps in both modes) and values in 32x documentation (as posted here)
I love when everything starts to fit correctly
Last edited by Eke on Fri Feb 20, 2009 3:27 pm, edited 5 times in total.
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Yup. The math seems to be correct, I've made them myself too.
S1 and S2 have HINT in water levels;
S2 has a 256 pixel display in the special stages and an interlace mode 2 in 2players vs;
Ecco2 EU has a 240 line display in some levels and HINTs in 3D stages.
S1 and S2 have HINT in water levels;
S2 has a 256 pixel display in the special stages and an interlace mode 2 in 2players vs;
Ecco2 EU has a 240 line display in some levels and HINTs in 3D stages.
Last edited by Jorge Nuno on Sat Feb 14, 2009 12:14 am, edited 1 time in total.
Hmm, I'd like to see this stuff specifically tested in H32 mode. It seems to me the timing is a little different, but you'd really need a scope to tell for sure. It's probably not different enough to be important, but stillEke wrote:(43 "H40" pixels and 30 "H32" pixels)
The stuff I wanted testing isn't really important either, more just 'out of interest', and has to do with vdp activity during the vblank area.
(not so) surprisingly, this somehow matches the TMS9918 documentation:
you can see that:
1/ right border + right blank is still 23 pixels count: however, this is meant to be 15 +8 pixels, not 14 +9 pixels as you measured...
2/ left border is still 13 pixels count
a few more maths about Hint: according to a sega bulletin, Hint is triggered 14.7 us before Vint which is approx. 790 Mcycles
this would mean Hint is approx. triggered 790 - (3*5 + 37*4 + 7*4 + 57*5 + 18*4 + 28*4) = 130 Mcycles before HBLANK (start of the right border)
also note that if the right border is 15 pixels (instead of 14) and the right blank is 8 pixels (instead of 9), this would mean HINT occurs approx. 250 Mcycles before the end of the right border
and 250 Mcycles = approx. 36 CPU cycles which is also a value used in offcial docs
you can see that:
1/ right border + right blank is still 23 pixels count: however, this is meant to be 15 +8 pixels, not 14 +9 pixels as you measured...
2/ left border is still 13 pixels count
a few more maths about Hint: according to a sega bulletin, Hint is triggered 14.7 us before Vint which is approx. 790 Mcycles
this would mean Hint is approx. triggered 790 - (3*5 + 37*4 + 7*4 + 57*5 + 18*4 + 28*4) = 130 Mcycles before HBLANK (start of the right border)
also note that if the right border is 15 pixels (instead of 14) and the right blank is 8 pixels (instead of 9), this would mean HINT occurs approx. 250 Mcycles before the end of the right border
and 250 Mcycles = approx. 36 CPU cycles which is also a value used in offcial docs
Last edited by Eke on Mon Feb 16, 2009 3:25 pm, edited 1 time in total.