Questions About Megadrive Chips/Signal

Ask anything your want about Megadrive/Genesis programming.

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mickagame
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Questions About Megadrive Chips/Signal

Post by mickagame » Tue May 31, 2022 9:43 am

1) Version Register is mapped into M68000 space to access some informations :
$A10000 $A10001 Version register
=> Where is located physically this register? In Bus Arbiter Chip?

2) Always in M68000 space : an address can be used to reset Z80 :
$A11200 $A11201 Z80 reset
=> What chips is involved in this operation? What chip catch the address and set the signal to the Z80Reset pin?

TmEE co.(TM)
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Re: Questions About Megadrive Chips/Signal

Post by TmEE co.(TM) » Tue May 31, 2022 10:01 am

Z80 bus request and reset come from bus chip, using the single data line that is connected to it. Z80 banker also is done by that chip, one bit at a time.

Version register with its many bits comes from the IO chip, and !FDC (MCD presence) and region signals also connect to it.

IO chip has all data lines of both buses connected and is instrumental in bus crossings using !ZTOV and !VTOZ signals. !IO signal that is fed by bus chip activates it. Bus chip has most of the address lines connected and does the primary address decode, but it has only one data line connected so any registers it has are 1 bit wide. Remaining address lines connect to IO chip and together they pass all of the address lines between the two buses.
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mickagame
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Re: Questions About Megadrive Chips/Signal

Post by mickagame » Tue May 31, 2022 11:12 am

TmEE co.(TM) wrote:
Tue May 31, 2022 10:01 am
Z80 bus request and reset come from bus chip, using the single data line that is connected to it. Z80 banker also is done by that chip, one bit at a time.

Version register with its many bits comes from the IO chip, and !FDC (MCD presence) and region signals also connect to it.

IO chip has all data lines of both buses connected and is instrumental in bus crossings using !ZTOV and !VTOZ signals. !IO signal that is fed by bus chip activates it. Bus chip has most of the address lines connected and does the primary address decode, but it has only one data line connected so any registers it has are 1 bit wide. Remaining address lines connect to IO chip and together they pass all of the address lines between the two buses.
Very Clear !

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