VPA Signal in interrupt process
Moderator: BigEvilCorporation
VPA Signal in interrupt process
VPA Signal is used during interrupt process by 68000 to use autovector insted vector read on bus. What component on megadrive generate this signal? I guess the signal is driven by 315-5364. When it turns the signal to low? I see that FC0/FC1 goes to 315-5364. I know that in interrupt process 68000 put all FC signal to high to request vector. It could be this signal that trigger 315-5364 put VPA to Low?
Same question for VPA going back to high. What signal captured by 315-5364 trigger this?
Thanks for your help
Same question for VPA going back to high. What signal captured by 315-5364 trigger this?
Thanks for your help
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Re: VPA Signal in interrupt process
It is driven by 315-5308/5364/5402/5433 and it should be response to FCx pins which also connect to these chips. I don't know any further details though...
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Re: VPA Signal in interrupt process
The hardware asserts VPA for the duration of the interrupt acknowledge cycle when AS is low and FC1, FC0 are high. See figure 5-10 and 5-11 here (note "IACK CYCLE" in the right half of 5-11) in the manual to see what the timing looks like.
https://www.nxp.com/docs/en/reference-m ... 8000UM.pdf
It doesn't need to check FC2 as the combination FC[2:0]=011 can't happen on a 68000, so it's sufficient to check the lower two bits. (not necessarily true for a 68010 or higher)
https://www.nxp.com/docs/en/reference-m ... 8000UM.pdf
It doesn't need to check FC2 as the combination FC[2:0]=011 can't happen on a 68000, so it's sufficient to check the lower two bits. (not necessarily true for a 68010 or higher)
Re: VPA Signal in interrupt process
Thanks Charles. Do you know what make the bus arbitrer release VPA?
1) The Bus arbitrer generate the signal during an amount of time?
2) Or VPA is released when FC1/FC0 goes low again?
1) The Bus arbitrer generate the signal during an amount of time?
2) Or VPA is released when FC1/FC0 goes low again?
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Re: VPA Signal in interrupt process
The last time I looked at this I didn't see any delays added by the hardware. As soon as the interrupt acknowledge cycle ends and AS goes high, then VPA is no longer asserted.
In theory this cycle lasts until it is terminated by VPA, BERR, or DTACK so it could be longer than four clocks but I've never seen the timing change. Are you observing anything different though? Some strange behavior?
In theory this cycle lasts until it is terminated by VPA, BERR, or DTACK so it could be longer than four clocks but I've never seen the timing change. Are you observing anything different though? Some strange behavior?
Re: VPA Signal in interrupt process
No i'm trying to understand how it works because i'm trying to emulate this as accurate as possible.
Do you know if the bus arbitrer chips works with an input signal clock or is just made of logical gate setting output signals depending on input signal?
Do you know if the bus arbitrer chips works with an input signal clock or is just made of logical gate setting output signals depending on input signal?
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Re: VPA Signal in interrupt process
I'd guess it's just combinatorial logic but I'd agree that we should get a definitive answer in case it isn't. When I have some free time I'll see if I can test this and let you know.
Re: VPA Signal in interrupt process
It coule be interesting. I dont have the material required to do this.