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The version register in IO Chip give informations like :

Bit(7) : Mode => Pin /LANG from IO Chip (can be set by jumper)
Bit(6) : VMode => Pin /PAL from IO Chip (can be set by jumper)
Bit(5) : Disk => Pin /DISK from IO Chip
Bit(4) : Reserved
Bit(3-0) : Version => ???

Is there any signal from IOChip corresponding to Bit(3-0) or value are stored inside the chip?

Verison part is hardwired to 0001 on all hardware I have seen (that has TMSS)

Yeah, it's zero on a 315-5309 IO chip and 1 on the 315-5402 (integrated IO chip and arbiter on a VA5) and all later IO chip versions. The 315-5402 doesn't have a full TMSS implementation though. Attempting to bank in the TMSS ROM will lock the machine (assuming because !DTACK is not being asserted for that address)

Ok thanks for this informations
The value is hardwired inside the chip or come from external (by a jumper for example)?

Right, 315-5402 is special, it shows no TMSS when in JP mode, while TMSS is shown in EN mode. I did notice the freezing problem with TMSS as I tried to dump the ROM when accessing the banking register...

The value is not adjustable externally.

TmEE co.(TM) wrote: ↑

Tue Feb 16, 2021 11:48 am

Right, 315-5402 is special, it shows no TMSS when in JP mode, while TMSS is shown in EN mode. I did notice the freezing problem with TMSS as I tried to dump the ROM when accessing the banking register...

Interesting. Were systems with the 315-5402 were actually released outside of Japan, or is this just from testing Japanese units with a region mod?

I have only ever seen the chip in Japanese machines, never in EU or US ones. I have the chip transplanted onto an EU VA5/6 board and the region mod changes TMSS behaviour. l_oliveira has some observations done too in past, telling that "SEGA" write is unnecessary when the language setting is in JP instead of EN (50/60 has no effect).