VDP Interrupt Processing

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mickagame
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VDP Interrupt Processing

Post by mickagame » Wed Feb 03, 2021 8:13 pm

I have a question about vdp interrupt processing.
How long the vdp assert interrupt line for Horizontal and Vertical Interrupt?

Stef
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Re: VDP Interrupt Processing

Post by Stef » Thu Feb 04, 2021 10:15 am

As long as M68K CPU acknowledge them.. if it doesn't then they remain pending indefinitely.
I don't think we can cancel them from VDP side.

mickagame
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Re: VDP Interrupt Processing

Post by mickagame » Thu Feb 04, 2021 10:31 am

So in my comprehension :
- The VDP lower the interrupt line
- When receive IACK from cpu the vdp raise interrupt line

This is correct?

So if VDP lower interrupt line and raise it before the CPU go in interrupt process the interrupt could be ignored (so pending interrupt == interrupt line in low state)?
If the vdp never raise the interrupt line the cpu will indefinitely execute the interrupt routine?

This extract from MC68000 manual seems to be confirm this behavior :
IPL0, IPL1, IPL2

These input indicate the encoded priority level of the device requesting an interrupt; Level seven is the highest priority while level 0 indicates that no interrupts are requested.
Level seven cannot be masked. The least significant bitis given in IPL0 and the most significant bit is contained in iPL2.
These lines must remain stable until the processor signals interrupt acknowledge (FC0-FC2 are all high) to insure the interrupt is recognized.
The way i understand is there is nothing inside processor that memoriez an interrupt is pending or not. It depends the stat of the IPL line.

Stef
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Re: VDP Interrupt Processing

Post by Stef » Fri Feb 05, 2021 1:18 pm

Yeah, that is how it works :)

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