M68K Bus Control and Vdp

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mickagame
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M68K Bus Control and Vdp

Post by mickagame » Sun Dec 08, 2019 1:42 pm

I have a question about the vdp/68K connection.

The VDP is connected to UDS/LDS signal from the 68K.
What the consequence for the vdp internally, for example, of reading upper byte (UDS = 0, LDS = 1) of Control/Data or HVC Counter?

Does the VDP return only upper byte on the D15-D8 data line and doesn't set the D7-D0 line?

Miquel
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Re: M68K Bus Control and Vdp

Post by Miquel » Sun Dec 08, 2019 10:44 pm

It will be unnecessarily more complicated doing so.
But what’s really the difference of setting those lines with known values or not: either case will be ignored.
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mickagame
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Re: M68K Bus Control and Vdp

Post by mickagame » Mon Dec 09, 2019 6:20 am

Is this the way i emulate my vdp access :

Code: Select all

u32 Vdp::readWord(u32 adress, u32 ctrl)

The method return D15-D0 lines (Word)
U32 adress : A24-A1 lines adress (A0 is bit 0 but is ignored)
u32 ctrl : Bit 0 : LDS, Bit 1 : UDS

Let's take an example of reading upper byte from Control data port from the 68K side (<=> readByte from the even adress)

Code: Select all

data = vdp->readWord(0xC00004, UDS);   /* UDS = 1 (Bit 0 = 1 (LDS High, UDS Low)) */
data = data >> 8;
Whatever UDS/LDS, the VDP will returns the control port fully on the data line.
Is this the behavior of the real hardware?

All this things is not very important but i want my code design reflect the real hardware.

Miquel
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Re: M68K Bus Control and Vdp

Post by Miquel » Mon Dec 09, 2019 2:56 pm

From real hardware perspective I don’t know if VDP registers take into account UDS/LDS signals or not.

What I know is that is not necessary at all, doing so only will waste chip gates.

All memory access are 16 bit access, and then on a byte operation the 68K uses the upper or lower byte ONLY. Therefor doesn’t matter at all what the content of the other byte is.

Your code seems perfect to me.

The idea of UDS/LDS signals is not announce if it is a byte operation or not, that could be done with only one signal, but to avoid hardware inconsistencies, like high impedance, when accessing 8 bit devices. It’s not a software problem, you can ignore it.
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mickagame
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Re: M68K Bus Control and Vdp

Post by mickagame » Mon Dec 09, 2019 6:02 pm

From my point of view when uds is selected the 68k put the upper byte of data bus into lower byte of register.

Miquel
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Re: M68K Bus Control and Vdp

Post by Miquel » Mon Dec 09, 2019 6:30 pm

Which register are you talking about, vdp register or cpu register?
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mickagame
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Re: M68K Bus Control and Vdp

Post by mickagame » Mon Dec 09, 2019 6:53 pm

I'm talking about the cpu register.
When you do read access with upper byte the cpu take the upper byte (D15-D8) from the bus and put this byte into lower byte of register.

Now, at the contrary, what happen if you do write access to vdp control port with
- UDS selected (<=> write byte at even adress)?
- LDS selected (<=> write byte at odd adress)?

Miquel
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Re: M68K Bus Control and Vdp

Post by Miquel » Mon Dec 09, 2019 7:56 pm

For all I know, when the 68k reads something it stores the data into the data register as is in the data bus, in the next cycle, when it moves it to some other part (alu or general use registers, for example) on the exit of the data register it can swap bytes if needed.

When it’s time to write…I have my doubts, I should look at documentation before anything else, but in this case UDS/LDS tells which byte(s) is valid and which (if any) is garbage…. I believe.
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mickagame
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Re: M68K Bus Control and Vdp

Post by mickagame » Mon Dec 09, 2019 8:05 pm

From Genesis Plus GX Source :

Code: Select all

void vdp_write_byte(unsigned int address, unsigned int data)
{
  switch (address & 0xFC)
  {
    case 0x00:  /* Data port */
    {
      vdp_68k_data_w(data << 8 | data);
      return;
    }

    case 0x04:  /* Control port */
    {
      vdp_68k_ctrl_w(data << 8 | data);
      return;
    }

    case 0x10:  /* PSG */
    case 0x14:
    {
      if (address & 1)
      {
        psg_write(m68k.cycles, data);
        return;
      }
      m68k_unused_8_w(address, data);
      return;
    }
I understand (if it's correct) that doing byte is only valid at even adress and is equivalent of doing word access with lower byte duplicated into upper byte.

My first question : It's correct?
Second Question : if it's correct what is the cause? Does the 68K duplicate lower byte when doing byte access at odd adress (And Why not duplicate upper byte when doing byte access at even address ...)?

Miquel
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Re: M68K Bus Control and Vdp

Post by Miquel » Mon Dec 09, 2019 10:20 pm

No, you can write bytes from the 68k both at even and odd address.

Documentation says (m68k.pdf):
68k byte Write Cycle: “STORE DATA ON D7–D0 IF LDS IS ASSERTED. STORE DATA ON D15–D8 IF UDS IS ASSERTED”

So in theory the other byte is in unknown value. I could be that the byte is duplicated by the 68k to increase compatibility, a bit weird, but could be. I don’t know for sure. But if it is duplicated is always duplicated both for even and odd address on byte writes.

Anyway accessing the VDP in byte mode is “prohibited” by Sega and I never used it because makes no sense.
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Re: M68K Bus Control and Vdp

Post by TmEE co.(TM) » Mon Dec 09, 2019 10:29 pm

68K duplicates high and lwo bytes during 8bit writes (i.e $12 is $1212 on the bus). Reads are aways 16bit and CPU internally chooses which half to use depending on address.
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mickagame
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Re: M68K Bus Control and Vdp

Post by mickagame » Tue Dec 10, 2019 6:22 am

TmEE co.(TM) wrote:
Mon Dec 09, 2019 10:29 pm
68K duplicates high and lwo bytes during 8bit writes (i.e $12 is $1212 on the bus). Reads are aways 16bit and CPU internally chooses which half to use depending on address.
That make sens.

From design code point of view this behavior have to be in my 68K core code, not in my vdp code.

Code: Select all

if (addr & 1) 68Kbus->write((data << 8) | data), LDS)
if (addr & 1) 68Kbus->write((data << 8) | data), UDS)

mickagame
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Re: M68K Bus Control and Vdp

Post by mickagame » Tue Dec 10, 2019 6:43 pm

mickagame wrote:
Tue Dec 10, 2019 6:22 am
TmEE co.(TM) wrote:
Mon Dec 09, 2019 10:29 pm
68K duplicates high and lwo bytes during 8bit writes (i.e $12 is $1212 on the bus). Reads are aways 16bit and CPU internally chooses which half to use depending on address.
That make sens.

From design code point of view this behavior have to be in my 68K core code, not in my vdp code.

Code: Select all

if (addr & 1) 68Kbus->write((data << 8) | data), LDS)
else 68Kbus->write((data << 8) | data), UDS)

8bitwizard
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Re: M68K Bus Control and Vdp

Post by 8bitwizard » Wed Dec 11, 2019 4:57 am

Remember that it needs to support byte access so the Z80 can talk to it a byte a time in SMS mode.

mickagame
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Re: M68K Bus Control and Vdp

Post by mickagame » Wed Dec 11, 2019 6:14 am

Another question about accessing Z80 space from 68K side :

From what i understand :
- If UDS selected byte will be read at even adress from Z80 bus (addr + 0) and will be returned at upper byte from 68K Bus (D15-D8)
- If LDS selected byte will be read at even adress from Z80 bus (addr + 1) and will be returned at lower byte from 68K Bus (D7-D0)

It's correct way to understand?

In this case, when UDS AND LDS are selected (Word Access) the system need to perform 2 bytes operations on Z80 bus before 68K can take the datas on the bus?

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