68K inner workings

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Gigasoft
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Posts: 95
Joined: Fri Jan 01, 2010 2:24 am

68K inner workings

Post by Gigasoft » Fri Jan 04, 2019 8:46 pm

Hi, I just wanted to share some of my notes I made a while back. This is based on Galibert's schematic, so in these notes the chip is assumed to be oriented such that the A13 pin is on the upper left. A lot of this is probably well known already, but I thought it'd be nice to have it all in one place.

On the left side of the chip we find the registers and their associated data processing circuitry. It is divided into three sections that can be connected together, each containing two separate lanes for transferring data. This means that the chip can execute up to 6 general purpose data transfers per cycle.

In addition to the architecturally visible registers, there are seven general purpose registers for use by the microcode, which I have given the names A through G.
- Register A is a 32-bit register that can be used as a memory address, and can be copied into PC. It can be loaded with the sum of two registers, or one register plus or minus a constant, which can be 4, 2 or the size specified by the current instruction.
- Register B is a 32-bit register that can retrieve the last accessed memory address (LAST).
- Register C is a 16-bit register that can retrieve an ALU result and be written to memory.
- Register D is a 16-bit register that can be loaded from memory.
- Register E is a 16-bit register that can be the second operand of an ALU operation.
- Register F is a 16-bit register that can be loaded with the immediate field of an instruction (IMM), the requested interrupt level (IPL), the status register (SR), the current instruction (IR), the current function code (FC), or an exception vector (Vec). It can also be copied into the status register (SR or CCR).
- Register G is a 16-bit shift register.
- There is also a 32-bit register that holds an immediate value.

From the top, we have:
(High section)
- high D0-D7, A0-A6, USP, SSP, immediate register, memory address register, A, PC.
- high adder
- high B
(Low section)
- low adder
- low A, PC, memory address register
- MOVEM register list (List)
- next bit in register list
- F
- low immediate register, SSP, USP, A6-A0
(Data section)
- low B, D7-D0
- Bit selection register (BIT#)
- Selected bit (BIT)
- D
- Output register
- G, C
- ALU flag output: carry 16, overflow 16, sign, carry 8, overflow 8, carry 4
- ALU
- ALU operands
- E

The vertical section in the center of the chip takes the current instruction as an input, and determines such things as instruction operands and exception vectors. This also extracts fields such as shift counts or the target of a branch instruction. The slightly wider section at the bottom selects which ALU functions to perform. Below this is the ALU control logic, with the CCR at the upper left.

At the bottom of the chip is the instruction decoder, which outputs a 10-bit microcode starting address. The left side determines whether an instruction is word or long sized. Instructions can consist of up to three stages, so above this is another instruction decoder. The left side recognizes invalid instructions, and the right side outputs addresses for the second and third stage of the instruction.

Above the invalid instructions we have the condition code evaluator. This produces two bits that form part of the next microcode address for a branching microcode instruction.

The large ROM on the right side of the chip contains the microcode. It is divided into two sections, each with their own address decoding. The left section produces a 68-bit output which specifies the operations to perform. The right section produces a 17-bit output which contains the next microcode address and a few other control bits. Some addresses may map to the same column in one or both sections, thus allowing operation words to be reused. You'll see some redundant operations throughout the code because of this.

To the right of the microcode, at the very top, is the 8-bit bus state machine. At the bottom is a circuit that determines which exception to raise, and the microcode address to jump to, based on which conditions are present at certain points during execution. At the very bottom right is the logic that handles the bus during 16-bit operation. I haven't deciphered how this one works yet.

On the VPA pin you'll notice a funny little circuit. Somehow, using the VPA pin, perhaps with a voltage outside the normal operational range, you can activate a test mode which outputs the 68-bit operation word on the address pins. Presumably, the instruction is input with the data pins, while selecting one of the three stages with IPL0 and DTACK. BR and BGACK control which branch to take for a branching instruction. IPL1 and IPL2 select which part of the operation word to output.

Let's look at some microcode. In the following, each step will appear on one line, with a list of operations performed during the step.
"x<=y" indicates that the previous value of y is copied into x, with sign extension where appropriate. "x.H" and "x.L" indicate the high or low part of a register. "x:y" indicates the 32-bit value formed by concatenating x with y. "[s:x]" indicates memory location x in address space s, where s is either DATA, PROGRAM or ACK. If an address is suffixed with ".B", it is accessed in byte mode if the current instruction is a byte instruction. Multiple registers may be given as a transfer destination, separated with commas. If an address appears alone, the address is prefetched. Math1, Math2 and Math3 invokes the ALU to perform an operation which differs depending on the instruction. Am/Dm/Rm refer to the register selected by the register field of an instruction, or the immediate register in the case of addq, subq, dbcc, trapcc, scc or an immediate ALU instruction. An/Dn/Rn refer to the register in the EA field, or the immediate register if an immediate or absolute addressing mode is used. Xn refers to the index register of an indexed addressing mode.

Other words that may appear on a line are:
FETCH - load next instruction word from prefetch buffer
PREFETCH[x] - prefetch instruction word from x
UPPER, LOWER - transfer upper or lower byte only
NEXT - get the next register of a MOVEM instruction
INT - load IPL, set S, clear T, no trace
FAULT - set S, clear T, no trace
TRAP - set S, clear T
RESET - assert the reset signal
HALT - assert the halt signal
CHECK - check for exception conditions
NEXTI - check interrupts, trace, illegal instruction etc.
End - end the current instruction
Stage2 - go to stage 2
Stage3 - go to stage 3

I'll start with the code that deals with various exceptional conditons.

Code: Select all

Exceptions:
 (1)  F<=SR A<=PC-2
 (2)  PC<=A C<=A.L FAULT A<=SSP-2
 (3)  C<=F [DATA:A]<=C A<=A-4
 (4)  SSP<=A C<=PC.H [DATA:A]<=C F<=Vec A<=A+2
 (5)  B<=F C<=E [DATA:A]<=C A<=A-4
 (6)  PC<=B D<=[DATA:B] A<=B+2
 (7)  B.H<=D D<=[DATA:A] A<=A+2
 (8)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
 (9) 
 (10)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (11)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End
Interrupt:
 (1)  F<=SR A<=PC-2
 (2)  PC<=A E<=F C<=A.L INT
 (3)  F<=IPL A<=SSP-2
 (4)  B<=F C<=E [DATA:A]<=C A<=A-4
 (5)  PREFETCH[ACK:B]
 (6)  CHECK
 (7)  FETCH F<=IMM
 (8)  SSP<=A C<=PC.H [DATA:A]<=C F<=Vec A<=A+2
 (9)  B<=F C<=E [DATA:A]<=C A<=A-4
 (10)  PC<=B D<=[DATA:B] A<=B+2
 (11)  B.H<=D D<=[DATA:A] A<=A+2
 (12)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
 (13) 
 (14)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (15)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End
Bus error:
 (1)  B<=LAST F<=SR A<=PC
 (2)  PC<=A C<=A.L FAULT A<=SSP-2
 (3)  C<=F [DATA:A]<=C A<=A-4
 (4)  C<=PC.H [DATA:A]<=C F<=IR A<=A+2
 (5)  C<=F [DATA:A]<=C A<=A-4
 (6)  PC<=B C<=B.L [DATA:A]<=C FETCH F<=FC A<=A-2
 (7)  C<=F [DATA:A]<=C A<=A-4
 (8)  SSP<=A C<=PC.H [DATA:A]<=C F<=Vec A<=A+2
 (9)  B<=F C<=E [DATA:A]<=C A<=A-4
 (10)  PC<=B D<=[DATA:B] A<=B+2
 (11)  B.H<=D D<=[DATA:A] A<=A+2
 (12)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
 (13) 
 (14)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (15)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End
Reset:
 (1) 
 (2)  FETCH F<=IMM
 (3)  F<=Vec
 (4)  INT A<=F
 (5)  SSP<=D D<=[PROGRAM:A] A<=A+2
 (6)  SSP<=D D<=[PROGRAM:A] A<=A+2
 (7)  SSP<=D D<=[PROGRAM:A] FAULT A<=A+2
 (8)  B.H<=D D<=[PROGRAM:A] A<=A+2
 (9)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
 (10) 
 (11)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (12)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End
Double fault:
 (1)  HALT
 Go to (1)
Reset+fault:
 (1)  HALT
 (2)  F<=SR A<=PC-2
 Go to (1)
As you can see, at the start of an instruction, the PC register points two bytes ahead of the current instruction, and the A register points four bytes ahead. The second word is in the prefetch queue and is also loaded into the D register, and F is loaded with the immediate field of the current instruction, if any. It is noteworthy that the reset routine fetches the initial SSP and PC from program memory rather than data memory like the other vectors. There is also an undocumented behaviour that occurs if a bus error occurs during reset processing, where the HALT signal will continuously toggle on and off.

Here are some examples of actual instructions.

Code: Select all

bclr Dm,Dn and the second phase of bclr #imm,Dn:
 (1)  B<=Rm BIT#<=Rm.L PC<=A A<=Rn CHECK [PROGRAM:A]
 (2)  E<=Rn.L C<=Math1(BIT,Rn.L) D<=[LAST] PREFETCH[LAST] A<=PC+2 NEXTI
 High word:
  (3)  E<=Rn.H C<=Math1(BIT,Rn.H)
  (4)  C<=Math3(BIT,C)
  (5)  Rn.H<=C C<=BIT&E CCR<=Flags.L FETCH F<=IMM
  End
 Low word:
  (6)  C<=Math3(BIT,C)
  (7)  Rn.L<=C C<=BIT&E CCR<=Flags.L FETCH F<=IMM
  End

Same for btst:
 (1)  B<=Rm BIT#<=Rm.L PC<=A A<=Rn CHECK [PROGRAM:A]
 (2)  E<=Rn.L C<=Rn.L D<=[LAST] PREFETCH[LAST] A<=PC+2 NEXTI
 High word:
  (3)  C<=BIT&Rn.H CCR<=Flags.L FETCH F<=IMM
  End
 Low word:
  (4)  Rn.L<=C C<=BIT&E CCR<=Flags.L FETCH F<=IMM
  End

scc Dn:
 (1)  PC<=A C<=0 NEXTI [PROGRAM:A]
 Condition false:
  (2)  Rn.L<=C D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2 W
  End
 Condition true:
  (3)  C<=Math1(-1,C) D<=[LAST] PREFETCH[LAST] A<=B
  (4)  Dn.L<=C FETCH F<=IMM A<=PC+2 W
  End

jsr.l:
 (1)  B.H<=D D<=[PROGRAM:A] A<=A+2
 (2)  B.L<=D PREFETCH[PROGRAM:B.H:D] PC<=A A<=Am-4
 (3)  [DATA:A]<=PC.H Rm<=A A<=A+2
 (4)  [DATA:A]<=PC.L A<=B+2 CHECK
 (5)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (6)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End
 
I have made a program which dumps all the instructions, but the output for complex instructions with a lot of branching needs to be polished a bit. More is to come. In the meantime, if someone needs to know how something works, feel free to ask.

Mask of Destiny
Very interested
Posts: 615
Joined: Thu Nov 30, 2006 6:30 am

Re: 68K inner workings

Post by Mask of Destiny » Sat Jan 05, 2019 9:09 pm

Have you had a look at the 68K patents? Looks like you've managed to figure out a lot from the schematic, but the US4325121 patent specifically has a lot of information about how the microcode/nanocode works and includes micro/nanocode listings for a pre-release version of the processor which might be useful for cross-referencing things. Oliver Galibert has also taken his own shot at decoding the micro/nanocode using mnemonics/labels from the patents which you can find here which might also be interesting to compare with.
Gigasoft wrote:
Fri Jan 04, 2019 8:46 pm
- Register A is a 32-bit register that can be used as a memory address, and can be copied into PC. It can be loaded with the sum of two registers, or one register plus or minus a constant, which can be 4, 2 or the size specified by the current instruction.
This sounds a lot like what the patents refer to as the address unit (referred to as au in the listings), or I guess the register that stores the result of address unit additions (listings don't really distinguish between the two).
Gigasoft wrote:
Fri Jan 04, 2019 8:46 pm
- Register B is a 32-bit register that can retrieve the last accessed memory address (LAST).
Based on the micro/nanocode you've listed, this might be what the patents call address temporary (at in the listings)
Gigasoft wrote:
Fri Jan 04, 2019 8:46 pm
- Register C is a 16-bit register that can retrieve an ALU result and be written to memory.
Not sure if this one has a separate name in the patents. In the listings, this is just referred to as if it's part of the ALU. (i.e. in places where you have an ALU op assigned to C, that transfer is implicit in the patent listings and in places that you list it as a source, the listings just use "alu").
Gigasoft wrote:
Fri Jan 04, 2019 8:46 pm
- Register D is a 16-bit register that can be loaded from memory.
This might be what the listings refer to as dbin, but I'm not sure
Gigasoft wrote:
Fri Jan 04, 2019 8:46 pm
- Register E is a 16-bit register that can be the second operand of an ALU operation.
I think this is referred to as alub in the listings.
Gigasoft wrote:
Fri Jan 04, 2019 8:46 pm
- Register G is a 16-bit shift register
I think this might be alue in the patent listings.
Gigasoft wrote:
Fri Jan 04, 2019 8:46 pm
- Bit selection register (BIT#)
- Selected bit (BIT)
I think the listings refer to these as dcr and (dcr) respectively.
Gigasoft wrote:
Fri Jan 04, 2019 8:46 pm
On the VPA pin you'll notice a funny little circuit. Somehow, using the VPA pin, perhaps with a voltage outside the normal operational range, you can activate a test mode which outputs the 68-bit operation word on the address pins. Presumably, the instruction is input with the data pins, while selecting one of the three stages with IPL0 and DTACK. BR and BGACK control which branch to take for a branching instruction. IPL1 and IPL2 select which part of the operation word to output.
According to a book quoted in this thread, the magic voltage is 8 volts. The pins used to control the output were a complete mystery though, so this is a really nice find.

The physical location of the various registers is also a very nice bit of work that I don't think there has been any public info on previously. The presence of result registers for the ALU and AU also explains how the 68K is able to safely read results of a previous operation in the same micro-cycle that it is supplying new parameters which is something I was wondering about.

Thanks for sharing your findings!

ijor
Interested
Posts: 15
Joined: Fri Nov 16, 2018 11:46 am

Re: 68K inner workings

Post by ijor » Mon Jan 07, 2019 12:26 pm

Gigasoft wrote:
Fri Jan 04, 2019 8:46 pm
Hi, I just wanted to share some of my notes I made a while back. This is based on Galibert's schematic, so in these notes the chip is assumed to be oriented such that the A13 pin is on the upper left. A lot of this is probably well known already, but I thought it'd be nice to have it all in one place.
Nice work. You definitely need to check the patents and the book already mentioned above :
https://www.amazon.com/Microarchitectur ... 940108775X

Note that as we discussed somewhere else, there seems to be at least one "trap" (copy protection) on the circuit and it's located at the bus arbitration state machine PLA.

Also check my signature if you are familiar with Verilog.
http://github.com/ijor/fx68k (68000 cycle accurate FPGA core)

ijor
Interested
Posts: 15
Joined: Fri Nov 16, 2018 11:46 am

Re: 68K inner workings

Post by ijor » Tue Jan 08, 2019 4:53 pm

Mask of Destiny wrote:
Sat Jan 05, 2019 9:09 pm
The physical location of the various registers is also a very nice bit of work that I don't think there has been any public info on previously. The presence of result registers for the ALU and AU also explains how the 68K is able to safely read results of a previous operation in the same micro-cycle that it is supplying new parameters which is something I was wondering about.
The physical location of the registers in the execution unit is described in the "Microarchitecture of VLSI computers" book mentioned above. I'm not sure, but I think Olivier also has this already labeled at the schematics in his tools.

Not sure how you thought ALU and AU could not be registered. If they were just combinatorial logic without storage, then they couldn't be used a transfer destination. If what you meant is that there are two separated sets of registers, AU result register in addition of AU register, then not, there is only one set of registers. The rest is just combinatorial logic.
http://github.com/ijor/fx68k (68000 cycle accurate FPGA core)

Gigasoft
Very interested
Posts: 95
Joined: Fri Jan 01, 2010 2:24 am

Re: 68K inner workings

Post by Gigasoft » Sun Feb 14, 2021 2:59 am

Here are the rest of the instructions.

Note: A.Count refers to bits 0-5 of the A register.

Instruction patterns without microcode:

Code: Select all

#0. XXXXXXXXXX1111X1 except #2, #3 illegal
#1. XXXXXXXXXX11111X except #2, #3 illegal
#2. 1110XXXXXXXXXXXX
#3. 011XXXXXXXXXXXXX
#4. 0000XXX011XXXXXX except #5 illegal
#5. XXXX100XXXXXXXXX
#6. 00001110XXXXXXXX illegal
#7. 0000XXXXXX11101X except #8, #9 illegal
#8. XXXX100000XXXXXX
#9. XXXXXXX100XXXXXX
#10. 0000XXXXXX111100 except #14, #11, #9 illegal
#11. XXXXX0100XXXXXXX
#12. 000XXXXXXX001XXX except #13 illegal
#13. XXX0XXX1XXXXXXXX
#14. XXXX00X00XXXXXXX
#15. 0001XXX001XXXXXX illegal
#16. 00XX1XX111XXXXXX except #18 illegal
#17. 00XXX1X111XXXXXX except #18 illegal
#18. XX00XXXXXXXXXXXX
#19. 0100001011XXXXXX illegal
#20. 010011X000XXXXXX illegal
#21. 010011000XXXXXXX illegal
#22. 0100XXXXXX001XXX except #24 illegal
#23. 0100XXXX0X11101X except #25 illegal
#24. XXXX111001XXXXXX
#25. XXXX1000X1XXXXXX
#26. 0100X0X01X11101X illegal
#27. 01000XX01011101X illegal
#28. XXXX01X011XXXXXX
#29. 0100XXXXXX111100 except #28, #30 illegal
#30. XXXXXXX110XXXXXX
#31. 0100XXX10XXXXXXX illegal
#32. 010011100111X100 illegal
#33. 01001000X1011XXX illegal
#34. 010010001X011XXX illegal
#35. 0100XXX111011XXX illegal
#36. 010011101X011XXX illegal
#37. 0100100001100XXX illegal
#38. 010011X01XX00XXX illegal
#39. 0100XXX111X00XXX illegal
#40. 0101XXXX00001XXX illegal
#41. 0101XXXXXX111X1X illegal
#42. 0101XXXXXX1111XX illegal
#43. 0111XXX1XXXXXXXX illegal
#44. 1000XXXXXX001XXX except #45 illegal
#45. XXXXXXX100XXXXXX
#46. 1XXXXXX10X11101X except #51 illegal
#47. 1XXXXXX1X011101X except #51 illegal
#48. 1XXXXXX10X1111XX except #51 illegal
#49. 1XXXXXX1X01111XX except #51 illegal
#50. 1000XXX101000XXX illegal
#51. 1110XXXXXXXXXXXX
#52. 1XX1XXX000001XXX illegal
#53. XXXXXXXXXXXXXXXX
#54. XXXXXXXXXXXXXXXX
#55. XXXXXXXXXXXXXXXX
#56. 11101XXX11XXXXXX illegal
#57. 1X00XXX0XX001XXX illegal
#58. 1X00XXX111001XXX illegal
#59. 1X00XXX110000XXX illegal
#60. 010011100110XXXX privileged
#61. 11100XXX1100XXXX illegal
#62. 11100XXX111111XX illegal
#63. 11100XXX11111X1X illegal
#64. 0000X0X001111100 privileged
#65. 010011100111001X privileged
#66. 01001110011100X0 privileged
#67. 0100011011XXXXXX privileged
#68. 0100111011111XXX illegal
#69. XXXXXXX010XXXXXX
#70. 0000XXXXXXXXXXXX
Instruction definitions are formatted like this:
I(Instruction number for stage 1) or A/B(Pattern number for stage 2 and 3) (Pattern) (W/L) (Exceptions) (Description)
W/L refers to instruction classes defined below.

Code: Select all

Byte/Word instruction class:
0000xxx1xxxxxxxx btst, bchg, bclr, bset dynamic
00x1xxxxxxxxxxxx move byte/word
0100xxx110xxxxxx chk word
0100xxx000xxxxxx link, nbcd
01000xx0x1xxxxxx move sr, negx, clr, neg, not byte/word
01001010x1xxxxxx tas, tst byte/word
1x00xxxx0xxxxxxx sbcd, abcd, exg, or, and byte
1x00xxxxx1xxxxxx divs, divu, muls, mulu, or, and word
1xx1xxxx0xxxxxxx subx, sub, cmpm, cmp, eor, addx, add byte
1xx1xxx0x1xxxxxx sub, cmp, eor, add word
0101xxxx0xxxxxxx addq, subq byte
0101xxxxx1xxxxxx addq, subq word, dbcc, trapcc, scc
11100xxx11xxxxxx memory shift

Long instruction class:
0010xxxxxxxxxxxx move long
01000xx010xxxxxx chk long
0100101010xxxxxx tst long
0101xxxx01xxxxxx addq, subq long
1x0xxxxx01xxxxxx or, and long
1xx1xxxx01xxxxxx subx, sub, cmpm, cmp, eor, addx, add long
1xx1xxxx11xxxxxx adda, suba


Undefined instructions (should never come here):
 (1)  B<=LAST F<=SR A<=PC
 (2)  HALT
 (3)  F<=SR A<=PC-2
 Go to (2)
 
 I0. XXXXXXXXXX111001L (Long at abs.l)
A86. 0000XXX010111001 except #72 (Immediate long to abs.l)
 (1)  B.H<=D D<=[PROGRAM:A] A<=A+2
 (2)  BIT#<=Dm.L B.L<=D D<=[PROGRAM:A] PREFETCH[PROGRAM:A] PC<=A A<=B.H:D W
 (3)  C<=D D<=[DATA:A] A<=A+2
 (4)  B<=A E,G<=D D<=[DATA:A] A<=PC+2
 Stage3

I1. XXXXXXXXXX111001W (Byte/Word at abs.l)
A87. 0000XXX0XX111001 except #86 (Immediate byte/word to abs.l)
 (1)  B.H<=D D<=[PROGRAM:A] A<=A+2
 (2)  BIT#<=Dm.L B.L<=D D<=[PROGRAM:A] PREFETCH[PROGRAM:A] PC<=A A<=B.H:D W
 (3)  C<=D D<=[DATA:B].B A<=PC+2
 Stage3

I2. XXXXXXXXXX111000L (Long at abs.w)
A84. 0000XXX010111000 except #72 (Immediate long to abs.w)
 (1)  BIT#<=Dm.L B<=D D<=[PROGRAM:A] PREFETCH[PROGRAM:A] PC<=A A<=D W
 (2)  C<=D D<=[DATA:A] A<=A+2
 (3)  B<=A E,G<=D D<=[DATA:A] A<=PC+2
 Stage3

I3. XXXXXXXXXX111000W (Byte/Word at abs.w)
A85. 0000XXX0XX111000 except #84 (Immediate byte/word to abs.w)
 (1)  BIT#<=Dm.L B<=D D<=[PROGRAM:A] PREFETCH[PROGRAM:A] PC<=A A<=D W
 (2)  C<=D D<=[DATA:B].B A<=PC+2
 Stage3

I4. XXXXXXXXXX010XXXL (Long at (An))
A71. 0000XXX010010XXX except #72 (Immediate long to (An))
 (1)  C<=D D<=[DATA:An] A<=An+2
 (2)  B<=A E,G<=D D<=[DATA:A] A<=PC+2
 Stage3

I5. XXXXXXXXXX010XXXW (Byte/Word at (An))
A73. 0000XXX0XX010XXX except #71 (Immediate byte/word to (An))
 (1)  B<=An C<=D [DATA:An].B
 (2)  BIT#<=Dm.L D<=[LAST].B W
 Stage3

I6. XXXXXXXXXX101XXXL (Long at d(An))
I7. XXXXXXXXXX111010L (Long at d(pc))
A78. 0000XXX010101XXX except #72 (Immediate long to d(An))
 (1)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=D+An
 (2)  C<=D D<=[A] A<=A+2
 (3)  B<=A E,G<=D D<=[A] A<=PC+4
 Stage3

I8. XXXXXXXXXX101XXXW (Byte/Word at d(An))
I9. XXXXXXXXXX111010W (Byte/Word at d(pc))
A79. 0000100000111010 (btst d(pc))
A80. 0000XXX0XX101XXX except #78 (Immediate byte/word to d(An))
 (1)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=D+An
 (2)  B<=A C<=D A<=PC+4 [A].B
 (3)  BIT#<=Dm.L D<=[LAST].B W
 Stage3

I10. XXXXXXXXXX110XXXL (Long at d(An, Xn))
I11. XXXXXXXXXX111011L (Long at d(pc, Xn))
A81. 0000XXX010110XXX except #72 (Immediate long to d(An, Xn))
 (1)  C<=D.B
 (2)  A<=An+C NEXTI [PROGRAM:A]
 Byte/Word Index:
  (3)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn.L+A
 Long Index:
  (4)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn+A
 (5)  C<=D D<=[A] A<=A+2
 (6)  B<=A E,G<=D D<=[A] A<=PC+4
 Stage3

I12. XXXXXXXXXX110XXXW (Byte/Word at d(An, Xn))
I13. XXXXXXXXXX111011W (Byte/Word at d(pc, Xn))
A82. 0000100000111011 (btst (An,Di))
A83. 0000XXX0XX110XXX except #81 (Immediate byte/word to address register with index)
 (1)  C<=D.B
 (2)  A<=An+C NEXTI [PROGRAM:A]
 Byte/Word Index:
  (3)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn.L+A
 Long Index:
  (4)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn+A
 (5)  B<=A C<=D A<=PC+4 [A].B
 (6)  BIT#<=Dm.L D<=[LAST].B W
 Stage3

I14. 1X00XXX100001XXX (sbcd, abcd -(An), -(Am))
 (1)  BIT#<=Dm.L E<=D PC<=A A<=An-Sz W
 (2)  An<=A Dn.L<=D C<=D [DATA:A].B
 (3)  D<=[LAST].B A<=Am-Sz
 (4)  Am,B<=A Dm.L,E<=D D<=[DATA:A].B CHECK
 (5)  C<=Math1(D,E) CCR<=Flags.L [PROGRAM:PC]
 (6)  C<=Math2(BCD,C) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H A<=B
 (7)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

I15. 1X01XXX110001XXX (subx.l, addx.l -(An), -(Am))
 (1)  BIT#<=Dm.L E<=D PC<=A A<=An-Sz W
 (2)  E<=D D<=[DATA:A] A<=A-2
 (3)  An<=A Dn.L<=D C<=D [DATA:A].B
 (4)  D<=[LAST].B A<=Am-Sz
 (5)  E<=D D<=[DATA:A] A<=A-2
 (6)  Am,B<=A Dm.L<=D C<=Math1(D,C) D<=[DATA:A] CCR<=Flags.L A<=A+2
 (7)  [DATA:A]<=C A<=D CHECK
 (8)  C<=Math2(D,E) D<=[PROGRAM:PC] PREFETCH[PROGRAM:PC] CCR<=Flags.H A<=B
 (9)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

I16. 1X01XXX10X001XXX (subx.b/w, addx.b/w -(An), -(Am))
 (1)  BIT#<=Dm.L E<=D PC<=A A<=An-Sz W
 (2)  An<=A Dn.L<=D C<=D [DATA:A].B
 (3)  D<=[LAST].B A<=Am-Sz
 (4)  Am,B<=A Dm.L,E<=D D<=[DATA:A].B CHECK
 (5)  C<=Math1(D,E) D<=[PROGRAM:PC] PREFETCH[PROGRAM:PC] CCR<=Flags.L A<=B
 (6)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

I17. 0100111001110001 (nop)
 (1)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (2)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I18. 0100101011000XXX (tas Dn)
 (1)  E<=Dn.L C<=Math1(Dn.L,F) PC<=A CHECK [PROGRAM:A]
 (2)  Rn.L<=C C<=E D<=[LAST] PREFETCH[LAST] CCR<=Flags.L FETCH F<=IMM A<=A+2 W
 End

I19. 010011100100XXXX (trap)
 (1)  F<=SR A<=PC-2
 (2)  C<=PC.L TRAP A<=SSP-2
 (3)  C<=F [DATA:A]<=C A<=A-4
 (4)  SSP<=A C<=PC.H [DATA:A]<=C F<=Vec A<=A+2
 (5)  B<=F C<=E [DATA:A]<=C A<=A-4
 (6)  PC<=B D<=[DATA:B] A<=B+2
 (7)  B.H<=D D<=[DATA:A] A<=A+2
 (8)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
 (9) 
 (10)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (11)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I20. 0100111001110110 (trapv)
 (1)  E<=D C<=Math1(BIT,D) F<=SR NEXTI [PROGRAM:A]
 Overflow:
  (2)  C<=PC.L D<=[LAST] TRAP A<=SSP-2
  (3)  C<=F [DATA:A]<=C A<=A-4
  (4)  SSP<=A C<=PC.H [DATA:A]<=C F<=Vec A<=A+2
  (5)  B<=F C<=E [DATA:A]<=C A<=A-4
  (6)  PC<=B D<=[DATA:B] A<=B+2
  (7)  B.H<=D D<=[DATA:A] A<=A+2
  (8)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
  (9) 
  (10)  PC<=A A<=A+2 CHECK [PROGRAM:A]
  (11)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 Not overflow:
  (12)  PC<=A D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=A+2
 End

I21. 0000XXX110000XXX (bclr Dm, Dn)
A93. 0000100010000XXX (bclr static Dn)
 (1)  B<=Rm BIT#<=Rm.L PC<=A A<=Rn CHECK [PROGRAM:A]
 (2)  E<=Rn.L C<=Math1(BIT,Rn.L) D<=[LAST] PREFETCH[LAST] A<=PC+2 NEXTI
 High byte/word:
  (3)  E<=Rn.H C<=Math1(BIT,Rn.H)
  (4)  C<=Math3(BIT,C)
  (5)  Rn.H<=C C<=BIT&E CCR<=Flags.L FETCH F<=IMM
 Low byte/word:
  (6)  C<=Math3(BIT,C)
  (7)  Rn.L<=C C<=BIT&E CCR<=Flags.L FETCH F<=IMM
 End

I22. 0000XXX1X1000XXX (bchg, bset Dm, Dn)
A90. 00001000X1000XXX (bchg, bset static Dn)
 (1)  B<=Rm BIT#<=Rm.L PC<=A A<=Rn CHECK [PROGRAM:A]
 (2)  E<=Rn.L C<=Math1(BIT,Rn.L) D<=[LAST] PREFETCH[LAST] A<=PC+2 NEXTI
 High byte/word:
  (3)  E<=Rn.H C<=Math1(BIT,Rn.H)
  (4)  Rn.H<=C C<=BIT&E CCR<=Flags.L FETCH F<=IMM
 Low byte/word:
  (5)  Rn.L<=C C<=BIT&E CCR<=Flags.L FETCH F<=IMM
 End

I23. 0100101010000XXX (tst.l Dn)
 (1)  B<=Rn PC<=A C<=Rn.L CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  C<=Rn.H D<=[LAST] PREFETCH[LAST] CCR<=Flags.H FETCH F<=IMM
 End

I24. 0000XXX100000XXX (btst Dm, Dn)
A89. 0000100000000XXX (btst static Dn)
 (1)  B<=Rm BIT#<=Rm.L PC<=A A<=Rn CHECK [PROGRAM:A]
 (2)  E<=Rn.L C<=Rn.L D<=[LAST] PREFETCH[LAST] A<=PC+2 NEXTI
 High byte/word:
  (3)  C<=BIT&Rn.H CCR<=Flags.L FETCH F<=IMM
 Low byte/word:
  (4)  Rn.L<=C C<=BIT&E CCR<=Flags.L FETCH F<=IMM
 End

I25. 0100XXX110000XXX (chk Dn)
A133. 0100XXX110XXXXXX (chk)
 (1)  E<=Dm.L C<=Math1(Dn.L,Dm.L) CCR<=Flags.L A<=A-2
 (2)  PC<=A C<=E CCR<=Flags.L A<=A+2 NEXTI
 Positive, not overflow:
  (3)  NEXTI
 Negative or overflow:
  (4)  F<=SR A<=PC-2
  (5)  C<=PC.L TRAP A<=SSP-2
  (6)  C<=F [DATA:A]<=C A<=A-4
  (7)  SSP<=A C<=PC.H [DATA:A]<=C F<=Vec A<=A+2
  (8)  B<=F C<=E [DATA:A]<=C A<=A-4
  (9)  PC<=B D<=[DATA:B] A<=B+2
  (10)  B.H<=D D<=[DATA:A] A<=A+2
  (11)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
  (12) 
 (13)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I26. 1011XXX10X001XXX (cmpm.b/w)
 (1)  PC<=A A<=An+Sz [DATA:An].B
 (2)  An,B<=A D<=[LAST].B A<=A+2
 (3)  C<=D D<=[DATA:Am].B A<=Am+Sz CHECK
 (4)  Am<=A Dm.L<=C C<=Math1(D,C) D<=[PROGRAM:PC] PREFETCH[PROGRAM:PC] CCR<=Flags.L FETCH F<=IMM A<=PC+2
 End

I27. 1011XXX110001XXX (cmpm.l)
 (1)  PC<=A A<=An+Sz [DATA:An].B
 (2)  An,B<=A D<=[LAST].B A<=A+2
 (3)  E<=D An<=A D<=[DATA:B]
 (4)  C<=D D<=[DATA:Am].B A<=Am+Sz CHECK
 (5)  G<=D D<=[DATA:A] A<=A+2
 (6)  Am<=A Dm.L<=C C<=Math1(D,C) CCR<=Flags.L A<=PC+2 [PROGRAM:PC]
 (7)  C<=Math2(G,E) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H FETCH F<=IMM
 End

I28. 1011XXX01000XXXX (cmp.l Rn, Dm)
I29. 1011XXX11100XXXX (cmpa.l Rn, Am)
A113. 1011XXX010XXXXXX (cmp.l)
A144. 1011XXX111XXXXXX (cmpa.l)
 (1)  B<=Rn.L C<=Math1(Rm.L,Rn.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  C<=Math2(Rm.H,Rn.H) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H
 (3)  FETCH F<=IMM A<=PC+2
 End

I30. 1011XXX01100XXXX (cmpa.b/w Rn, Am)
A146. 1011XXX011XXXXXX (cmpa.b/w)
 (1)  B<=Rn.L C<=Math1(Rm.L,Rn.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  C<=Math2(Rm.H,B.H) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H
 (3)  FETCH F<=IMM A<=PC+2
 End

I31. 1011XXX00X00XXXX (cmp.b/w Rn, Dm)
A145. 1011XXX00XXXXXXX (cmp.b/w)
 (1)  B<=Rn.L C<=Math1(Rm.L,Rn.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2
 End

I32. 0101XXXX11001XXX (dbcc)
 (1)  A<=D+PC NEXTI
 Condition false:
  (2)  B<=A E<=Dn.L C<=Dn.L A<=PC+2 [PROGRAM:A]
  (3)  C<=Math2(-1,E) PREFETCH[LAST] PC<=A A<=B+2 NEXTI
  Result not zero:
   (4)  D<=[PROGRAM:PC] PREFETCH[PROGRAM:PC] FETCH F<=IMM A<=PC+2
  (5)  PC<=A A<=A+2 CHECK [PROGRAM:A]
  (6)  Rn.L<=C D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2 W
 Condition true:
  (7)  FETCH F<=IMM A<=PC+2
  (8)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
  (9)  PC<=A A<=A+2 CHECK [PROGRAM:A]
  (10)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I33. 1000XXX111000XXX (divs Dn)
A142. 1000XXX111XXXXXX (divs)
 (1)  B.H<=Rn.L E<=Rn.L G<=Dm.L C<=Rn.L CCR<=Flags.L PC<=A
 (2)  C<=Math1(0,E) CCR<=Flags.L NEXTI
 Negative:
  (3)  B.L<=None E<=C C<=Rm.H CCR<=Flags.L A<=None:F+Sz Cy
  (4)  C<=Math1(0,Rm.L) NEXTI
  Positive:
   (5)  C<=Math1(B.L,E) CCR<=Flags.L
  Negative:
   (6)  G<=C C<=Math2(0,Rm.H)
   (7)  B.L<=C C<=Math1(C,E) CCR<=Flags.L
  (8)  C<=B.L CCR<=Flags.L NEXTI
  Carry:
   (9)  C<=Math3(-1,C) A<=A-Sz Cy
   (10)  B.L<=C C<=Math1(C,E) CCR<=Flags.L NEXTI
   A.Count != 0:
    (11)  NEXTI
    Carry:
     (12)  C<=B.L CCR<=Flags.L
     Go to (9)
    Not carry:
     (13)  C<=Math5(-1,C) A<=A-Sz Cy
     Go to (10)
   (14)  NEXTI
   Carry:
    (15)  C<=Math3(-1,C) A<=A-Sz Cy
   Not carry:
    (16)  B.L<=C C<=Math5(-1,C)
   (17)  C<=B.H CCR<=Flags.L
   (18)  E<=G C<=Rm.H CCR<=Flags.L NEXTI
   Positive:
    (19)  B.H<=B.L C<=E CCR<=Flags.L NEXTI
    Positive:
     (20)  B.L<=C C<=C CCR<=Flags.L A<=PC+2 NEXTI [PROGRAM:PC]
     Positive:
      (21)  Rm<=B D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2
      End
     Negative:
      (22)  C<=None|None.B D<=[LAST] PREFETCH[LAST] CCR<=Flags.L FETCH F<=IMM
      End
    Negative:
     (23)  C<=Math1(0,E) CCR<=Flags.L
     (24)  B.L<=C E<=C C<=Math1(0,B.H) NEXTI
     Zero:
      (25)  B.H<=C C<=E CCR<=Flags.L A<=PC+2 CHECK [PROGRAM:PC]
      Go to (21)
     Nonzero:
      (26)  A<=PC+2 CHECK [PROGRAM:PC]
      Go to (22)
   Negative:
    (27)  B.H<=B.L C<=E CCR<=Flags.L NEXTI
    Positive:
     (28)  C<=Math1(0,E) CCR<=Flags.L CHECK
     (29)  B.L<=C C<=C CCR<=Flags.L A<=PC+2 NEXTI [PROGRAM:PC]
     Zero: Go to (21)
     Nonzero: Go to (22)
    Negative:
     (30)  B.L<=C E<=C C<=Math1(0,B.H) NEXTI
     Positive: Go to (25)
     Negative: Go to (26)
  Not carry:
   (31)  A<=PC+2 CHECK [PROGRAM:PC]
   Go to (22)
 Positive:
  (32)  B.L<=None C<=Rm.H CCR<=Flags.L A<=None:F+Sz Cy
  Go to (4)
 Zero:
  (33)  F<=SR A<=PC-2
  (34)  PC<=A C<=A.L TRAP A<=SSP-2
  (35)  C<=F [DATA:A]<=C A<=A-4
  (36)  SSP<=A C<=PC.H [DATA:A]<=C F<=Vec A<=A+2
  (37)  B<=F C<=E [DATA:A]<=C A<=A-4
  (38)  PC<=B D<=[DATA:B] A<=B+2
  (39)  B.H<=D D<=[DATA:A] A<=A+2
  (40)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
  (41) 
  (42)  PC<=A A<=A+2 CHECK [PROGRAM:A]
  (43)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I34. 1000XXX011000XXX (divu Dn)
A141. 1000XXX011XXXXXX (divu)
 (1)  B.H<=Rn.L E<=Rn.L G<=Dm.L C<=Rn.L CCR<=Flags.L PC<=A
 (2)  C<=Math1(Rm.H,E) CCR<=Flags.L NEXTI
 Nonzero:
  (3)  B.L<=None C<=Rm.H CCR<=Flags.L A<=None:F+Sz NEXTI Cy
  Carry:
   (4)  C<=Math3(-1,C) A<=A-Sz NEXTI Cy
   Positive:
    (5)  B.L<=C C<=Math1(C,E) CCR<=Flags.L NEXTI
    A.Count = 0:
     (6)  Rm.H<=C C<=0 NEXTI
     Carry:
      (7)  Rm.H<=B.L E<=C C<=Math3(-1,C) A<=PC+2 CHECK [PROGRAM:PC]
      (8)  Rm.L<=G C<=Math1(G,E) D<=[LAST] PREFETCH[LAST] CCR<=Flags.L FETCH F<=IMM
      End
     Not carry:
      (9)  E<=C C<=Math5(-1,C) A<=PC+2 CHECK [PROGRAM:PC]
      Go to (8)
    A.Count != 0:
     (10)  NEXTI
     Carry:
      (11)  C<=B.L CCR<=Flags.L
      Go to (4)
     Not carry:
      (12)  C<=Math5(-1,C) A<=A-Sz NEXTI Cy
      Positive: Go to (5)
      Negative:
       (13)  B.L<=C C<=Math1(C,E) CCR<=Flags.L NEXTI
       A.Count = 0:
        (14)  Rm.H<=C C<=0
        Go to (9)
       A.Count != 0: Go to (12)
   Negative: Go to (13)
   Go to (8)
  Not carry:
   (15)  A<=PC+2 CHECK [PROGRAM:PC]
   (16)  C<=None|None.B D<=[LAST] PREFETCH[LAST] CCR<=Flags.L FETCH F<=IMM
   End
 Zero:
  (17)  F<=SR A<=PC-2
  (18)  PC<=A C<=A.L TRAP A<=SSP-2
  (19)  C<=F [DATA:A]<=C A<=A-4
  (20)  SSP<=A C<=PC.H [DATA:A]<=C F<=Vec A<=A+2
  (21)  B<=F C<=E [DATA:A]<=C A<=A-4
  (22)  PC<=B D<=[DATA:B] A<=B+2
  (23)  B.H<=D D<=[DATA:A] A<=A+2
  (24)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
  (25) 
  (26)  PC<=A A<=A+2 CHECK [PROGRAM:A]
  (27)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I35. 1100XXX10100XXXX (exg Dm,Dn or exg Am,An)
I36. 1100XXX110001XXX (exg Dm,An)
 (1)  B<=Rm BIT#<=Rm.L PC<=A A<=Rn CHECK [PROGRAM:A]
 (2)  Rm<=A Rn<=B D<=[LAST] PREFETCH[LAST]
 (3)  FETCH F<=IMM A<=PC+2
 End

I37. 0100100011000XXX (ext.l Dn)
 (1)  B<=Rn.L C<=Math2(-1,Rn.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rn<=B D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2
 End

I38. XXXXXXXXXX111100L (immediate long)
 (1)  Rn.H<=D D<=[PROGRAM:A] A<=A+2
 (2)  B.H<=D Rn.L<=D,None PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 Stage2

I39. XXXXXXXXXX111100W (immediate byte/word)
 (1)  B.H<=D Rn.L<=D,None PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 Stage2

I40. 0100111011111001 (jmp abs.l)
 (1)  B.H<=D D<=[PROGRAM:A] A<=A+2
 (2)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
 (3)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (4)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I41. 0100111011111000 (jmp abs.w)
 (1)  B<=D
 (2)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
 (3)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (4)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I42. 0100111011010XXX (jmp (An))
 (1)  PREFETCH[PROGRAM:An] A<=An+2
 (2)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (3)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I43. 0100111011101XXX (jmp d(An))
I44. 0100111011111010 (jmp d(pc))
 (1)  A<=D+An
 (2)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (3)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (4)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I45. 0100111011110XXX (jmp d(An, Xn))
I46. 0100111011111011 (jmp d(pc, Xn))
 (1)  C<=D.B
 (2)  A<=C+An NEXTI
 Byte/Word Index:
  (3)  A<=A+Xn.L
 Long Index:
  (4)  A<=A+Xn
 (5)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (6)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I47. 0100111010111001 (jsr abs.l)
 (1)  B.H<=D D<=[PROGRAM:A] A<=A+2
 (2)  B.L<=D PREFETCH[PROGRAM:B.H:D] PC<=A A<=Am-4
 (3)  [DATA:A]<=PC.H Rm<=A A<=A+2
 (4)  [DATA:A]<=PC.L A<=B+2 CHECK
 (5)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (6)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I48. 0100111010111000 (jsr abs.w)
 (1)  B<=D
 (2)  PREFETCH[PROGRAM:B] PC<=A A<=Am-4
 (3)  [DATA:A]<=PC.H Rm<=A A<=A+2
 (4)  [DATA:A]<=PC.L A<=B+2 CHECK
 (5)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (6)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I49. 0100111010010XXX (jsr (An))
 (1)  B<=An PREFETCH[PROGRAM:An] A<=Am-4
 (2)  [DATA:A]<=PC.H Rm<=A A<=A+2
 (3)  [DATA:A]<=PC.L A<=B+2 CHECK
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I50. 0100111010101XXX (jsr d(An))
I51. 0100111010111010 (jsr d(pc))
 (1)  A<=D+An
 (2)  B<=A A<=PC+2 [PROGRAM:A]
 (3)  PREFETCH[LAST] PC<=A A<=Am-4
 (4)  [DATA:A]<=PC.H Rm<=A A<=A+2
 (5)  [DATA:A]<=PC.L A<=B+2 CHECK
 (6)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I52. 0100111010110XXX (jsr d(An, Xn))
I53. 0100111010111011 (jsr d(pc, Xn))
 (1)  C<=D.B
 (2)  A<=C+An NEXTI
 Byte/Word Index:
  (3)  A<=A+Xn.L
 Long Index:
  (4)  A<=A+Xn
 (5)  B<=A A<=PC+2 [PROGRAM:A]
 (6)  PREFETCH[LAST] PC<=A A<=Am-4
 (7)  [DATA:A]<=PC.H Rm<=A A<=A+2
 (8)  [DATA:A]<=PC.L A<=B+2 CHECK
 (9)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (10)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I54. 0100XXX111111001 (lea abs.l, Am)
 (1)  Rm.H<=D D<=[PROGRAM:A] A<=A+2
 (2)  Rm.L<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (3)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (4)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I55. 0100XXX111111000 (lea abs.w, Am)
 (1)  Rm<=D PREFETCH[PROGRAM:A] A<=A+2
 (2)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (3)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I56. 010011001X101XXX (movem from d(An))
I57. 010011001X111010 (movem from d(pc))
 (1)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (2)  A<=D+An [PROGRAM:A]
 (3)  B<=A PREFETCH[LAST] A<=PC+4
 (4)  D<=[B] NEXT PC<=A A<=B+2 NEXTI
 Movem.w:
  (5)  Rm<=D B<=A D<=[A] NEXT A<=A+2 NEXTI
  Movem.w: Go to (5)
 Movem.l:
  (6)  Rm.H<=D D<=[A] A<=A+2
  (7)  Rm.L<=D B<=A D<=[A] NEXT A<=A+2 NEXTI
  Movem.l: Go to (6)
 (8)  A<=PC+2 CHECK [PROGRAM:PC]
 (9)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I58. 010011001X010XXX (movem from (An))
 (1)  List,F<=D D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (2)  B<=Rn D<=[DATA:Rn] NEXT PC<=A A<=Rn+2 NEXTI
 Movem.w:
  (3)  Rm<=D B<=A D<=[A] NEXT A<=A+2 NEXTI
  Movem.w: Go to (3)
 Movem.l:
  (4)  Rm.H<=D D<=[A] A<=A+2
  (5)  Rm.L<=D B<=A D<=[A] NEXT A<=A+2 NEXTI
  Movem.l: Go to (4)
 (6)  A<=PC+2 CHECK [PROGRAM:PC]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I59. 010011001X110XXX (movem from d(An, Xn))
I60. 010011001X111011 (movem from d(pc, Xn))
 (1)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (2)  C<=D.B
 (3)  A<=An+C NEXTI [PROGRAM:A]
 Byte/Word Index:
  (4)  PREFETCH[LAST] A<=Xn.L+A
 Long Index:
  (5)  PREFETCH[LAST] A<=Xn+A
 (6)  B<=A C<=D A<=PC+4 [A].B
 (7)  D<=[LAST] NEXT PC<=A A<=B+2 NEXTI
 Movem.w:
  (8)  Rm<=D B<=A D<=[A] NEXT A<=A+2 NEXTI
  Movem.w: Go to (8)
 Movem.l:
  (9)  Rm.H<=D D<=[A] A<=A+2
  (10)  Rm.L<=D B<=A D<=[A] NEXT A<=A+2 NEXTI
  Movem.l: Go to (9)
 (11)  A<=PC+2 CHECK [PROGRAM:PC]
 (12)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I61. 0100XXX111010XXX (lea (An), Am)
 (1)  List,F<=D B<=An PC<=A CHECK [PROGRAM:A]
 (2)  Rm<=B D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2
 End

I62. 0100XXX111101XXX (lea d(An), Am)
I63. 0100XXX111111010 (lea d(pc), Am)
 (1)  A<=D+An [PROGRAM:A]
 (2)  Rm<=A PREFETCH[LAST] A<=PC+4
 (3)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (4)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I64. 0100XXX111110XXX (lea d(An, Xn), Am)
I65. 0100XXX111111011 (lea d(pc, Xn), Am)
 (1)  C<=D.B
 (2)  A<=An+C NEXTI [PROGRAM:A]
 Byte/Word Index:
  (3)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn.L+A
 Long Index:
  (4)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn+A
 (5)  Rm<=A A<=PC+4
 (6)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I66. 0100111001010XXX (link)
 (1)  B<=Rn C<=Rn.L A<=A+2 [PROGRAM:A]
 (2)  PREFETCH[LAST] PC<=A A<=Am-4
 (3)  [DATA:A]<=B.H An<=A A<=A+2 CHECK
 (4)  [DATA:A]<=C A<=D+An
 (5)  Am<=A D<=[PROGRAM:PC] PREFETCH[PROGRAM:PC] FETCH F<=IMM A<=PC+2
 End

I67. 010011001X111001 (movem from abs.l)
 (1)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (2)  Rn.H<=D D<=[PROGRAM:A] A<=A+2
 (3)  B.H<=D Rn.L<=D,None PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (4)  B<=Rn D<=[DATA:Rn] NEXT PC<=A A<=Rn+2 NEXTI
 Movem.w:
  (5)  Rm<=D B<=A D<=[A] NEXT A<=A+2 NEXTI
  Movem.w: Go to (5)
 Movem.l:
  (6)  Rm.H<=D D<=[A] A<=A+2
  (7)  Rm.L<=D B<=A D<=[A] NEXT A<=A+2 NEXTI
  Movem.l: Go to (6)
 (8)  A<=PC+2 CHECK [PROGRAM:PC]
 (9)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I68. 010011001X111000 (movem from abs.w)
 (1)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (2)  Rn<=D PREFETCH[PROGRAM:A] A<=A+2
 (3)  B<=Rn D<=[DATA:Rn] NEXT PC<=A A<=Rn+2 NEXTI
 Movem.w:
  (4)  Rm<=D B<=A D<=[A] NEXT A<=A+2 NEXTI
  Movem.w: Go to (4)
 Movem.l:
  (5)  Rm.H<=D D<=[A] A<=A+2
  (6)  Rm.L<=D B<=A D<=[A] NEXT A<=A+2 NEXTI
  Movem.l: Go to (5)
 (7)  A<=PC+2 CHECK [PROGRAM:PC]
 (8)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I69. 0100111001100XXX (move Dn, usp)
 (1)  List,F<=D B<=An PC<=A CHECK [PROGRAM:A]
 (2)  Rm<=B D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2
 End

I70. 0000XXX101001XXX (movep.l d(An), Dm)
 (1)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=D+An
 (2)  D<=[DATA:A].B UPPER A<=A+2
 (3)  D<=[DATA:A].B LOWER A<=A+2
 (4)  Rm.H<=D D<=[DATA:A].B UPPER A<=A+2
 (5)  D<=[DATA:A].B LOWER A<=PC+4 CHECK
 (6)  Dm.L<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] FETCH F<=IMM A<=A+2
 End

I71. 0000XXX100001XXX (movep.w d(An), Dm)
 (1)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=D+An
 (2)  D<=[DATA:A].B UPPER A<=A+2
 (3)  D<=[DATA:A].B LOWER A<=PC+4 CHECK
 (4)  Dm.L<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] FETCH F<=IMM A<=A+2
 End

I72. 0000XXX111001XXX (movep.l Dm, d(An))
 (1)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=D+An
 (2)  [DATA:A].B<=Rm.H UPPER A<=A+2
 (3)  [DATA:A].B<=Rm.H LOWER A<=A+2
 (4)  [DATA:A].B<=Dm.L UPPER A<=A+2 CHECK
 (5)  [DATA:A].B<=Dm.L LOWER A<=PC+4
 (6)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I73. 0000XXX110001XXX (movep.w Dm, d(An))
 (1)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=D+An
 (2)  [DATA:A].B<=Dm.L UPPER A<=A+2 CHECK
 (3)  [DATA:A].B<=Dm.L LOWER A<=PC+4
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I74. 1100XXXX11000XXX (muls, mulu Dn)
A147. 1100XXXX11XXXXXX (muls, mulu)
 (1)  B<=A E<=Dm.L G<=Dn.L C<=0 CCR<=Flags.L A<=None:F CHECK [PROGRAM:A]
 (2)  Rm.L<=C D<=[LAST] PREFETCH[LAST] NEXTI
 1 unsigned:
  (3)  C<=Math2(C,E) CCR<=Flags.H
 1 signed:
  (4)  C<=Math1(C,E) CCR<=Flags.H
 (5)  PC.L<=B.L C<=Math3(-1,C) CCR<=Flags.H A<=A-Sz NEXTI Cy
 01 signed or 1x unsigned: Go to (3)
 10 signed: Go to (4)
 Neither: Go to (5)
 A. Count = 0:
  (6)  Rm.H<=C PC.H<=B.H Am.L<=B.L Dm.L<=G C<=C CCR<=Flags.H FETCH F<=IMM A<=B+2
  End

I75. X100100000000XXX (nbcd Dn)
 (1)  PC<=A C<=Math1(0,Rn.L) CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  C<=Math2(BCD,C) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H A<=B
 (3)  Dn.L<=C FETCH F<=IMM A<=PC+2 W
 End

I76. X1000XX010000XXX (negx.l, clr.l, neg.l, not.l Dn)
 (1)  PC<=A C<=Math1(0,Rn.L) CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  Rn.L<=C C<=Math2(0,Rn.H) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H
 (3)  Rn.H<=C FETCH F<=IMM A<=PC+2
 End

I77. X1000XX00X000XXX (negx.b/w, clr.b/w, neg.b/w, not.b/w Dn)
I78. X100100010000XXX (ext.w Dn)
 (1)  PC<=A C<=Math1(0,Rn.L) CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  Rn.L<=C D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2 W
 End

I79. X10010100X000XXX (tst.b/w Dn)
 (1)  B<=Rn PC<=A C<=Rn.L CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I80. X000XXX00XXXXXXX (eori.b/w, ori.b/w, andi.b/w, subi.b/w, add.b/w)
I147. 000010001XXXXXXX (bclr, bset static)
 (1)  Rm.L<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 Stage2

I81. X100111001011XXX (unlk)
 (1)  B<=Rn D<=[DATA:Rn] NEXT PC<=A A<=Rn+2
 (2)  B.H<=D D<=[DATA:A] A<=A+2 CHECK
 (3)  Rm<=A A<=PC+2 [PROGRAM:PC]
 (4)  Rn<=B.H:D D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I82. X100100001111001 (pea abs.l)
 (1)  B.H<=D D<=[PROGRAM:A] A<=A+2
 (2)  B.L<=D PREFETCH[PROGRAM:A] PC<=A A<=Am-4
 (3)  [DATA:A]<=B.H Rm<=A A<=A+2
 (4)  [DATA:A]<=B.L FETCH F<=IMM A<=PC+2
 (5)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (6)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I83. X100100001111000 (pea abs.w)
 (1)  B<=D PREFETCH[PROGRAM:A] PC<=A A<=Am-4
 (2)  [DATA:A]<=B.H Rm<=A A<=A+2
 (3)  [DATA:A]<=B.L FETCH F<=IMM A<=PC+2
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I84. XXXXXXXXXX100XXXL (predecrement long)
A76. 0000XXX010100XXX except #72 (immediate long to -(An))
 (1)  C<=D A<=An-4
 (2)  An<=A D<=[DATA:A] A<=A+2
 (3)  B<=A E,G<=D D<=[DATA:A] A<=PC+2
 Stage3

I85. XXXXXXXXXX100XXXW (predecrement byte/word)
A77. 0000XXX0XX100XXX except #76 (immediate byte/word to -(An))
 (1)  BIT#<=Dm.L E<=D PC<=A A<=An-Sz W
 (2)  An,B<=A C<=E D<=[DATA:A].B A<=PC
 Stage3

I86. 0100100001010XXX (pea (An))
 (1)  B<=Rn C<=Rn.L D<=[PROGRAM:A] PREFETCH[PROGRAM:A] PC<=A A<=Am-4 CHECK
 (2)  [DATA:A]<=B.H Rm<=A A<=A+2
 (3)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

I87. 0100100001101XXX (pea d(An))
I88. 0100100001111010 (pea d(pc)) 
 (1)  B<=An C<=D D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (2)  PC<=A A<=C+B CHECK [PROGRAM:A]
 (3)  B<=A C<=A.L D<=[LAST] PREFETCH[LAST] A<=Am-4
 (4)  [DATA:A]<=B.H Rm<=A A<=A+2
 (5)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

I89. 0100100001110XXX (pea d(An, Xn))
I90. 0100100001111011 (pea d(pc, Xn))
 (1)  C<=D.B
 (2)  A<=An+C NEXTI [PROGRAM:A]
 Byte/Word Index:
  (3)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn.L+A
 Long Index:
  (4)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn+A
 (5)  B<=A C<=A.L A<=PC+4 CHECK
 (6)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] PC<=A A<=Am-4
 (7)  [DATA:A]<=B.H Rm<=A A<=A+2
 (8)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

I91. XXXXXXXXXX011XXXL (Long at (An)+)
A74. 0000XXX010011XXX except #72 (immediate to postincrement long)
 (1)  C<=D D<=[DATA:An] A<=An+2
 (2)  B<=A E,G<=D A<=A+2 [DATA:A]
 (3)  An<=A D<=[LAST] A<=PC+2
 Stage3

I92. XXXXXXXXXX011XXXW (Byte/Word at (An)+)
A75. 0000XXX0XX011XXX except #74 (immediate to postincrement byte/word)
 (1)  BIT#<=Dm.L B<=An E<=D A<=An+Sz W [DATA:An].B
 (2)  An<=A C<=E D<=[LAST].B A<=PC+2
 Stage3

I93. 010011001X011XXX (movem from (An)+)
 (1)  List,F<=D D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (2)  B<=Rn D<=[DATA:Rn] NEXT PC<=A A<=Rn+2 NEXTI
 Movem.w:
  (3)  Rm<=D B<=A D<=[DATA:A] NEXT A<=A+2 NEXTI
  Movem.w: Go to (3)
 Movem.l:
  (4)  Rm.H<=D D<=[DATA:A] A<=A+2
  (5)  Rm.L<=D B<=A D<=[DATA:A] NEXT A<=A+2 NEXTI
   Movem.l: Go to (4)
 (6)  Rn<=B A<=PC+2 [PROGRAM:PC]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I94. 010010001X100XXX (movem to -(An))
 (1)  List,F<=D A<=A+2 [PROGRAM:A]
 (2)  B<=An PREFETCH[LAST] NEXT PC<=A A<=An-2 NEXTI
 Movem.w:
  (3)  [DATA:A]<=Rm.L B<=A NEXT A<=A-2 NEXTI
  Movem.w: Go to (3)
 Movem.l:
  (4)  [DATA:A]<=Rm.L B<=A A<=A-2
  (5)  [DATA:A]<=Rm.H B<=A NEXT A<=A-2 NEXTI
  Movem.l: Go to (4)
 (6)  Rn<=B A<=PC+2 CHECK [PROGRAM:PC]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I95. 001000111100XXXX (move.l Rn, abs.l)
 (1)  B.H<=D D<=[PROGRAM:A] A<=A+2
 (2)  B.L<=Rn.L C<=Rn.L PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=B.H:D
 (3)  E,[DATA:A]<=Rn.H C<=Rn.H CCR<=Flags.H A<=A+2
 (4)  [DATA:A]<=B.L FETCH F<=IMM A<=PC+2
 (5)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (6)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I96. 00X100111100XXXX (move.b/w Rn, abs.l)
A126. 00X1001111XXXXXX (move.b/w to abs.l)
 (1)  B.H<=D D<=[PROGRAM:A] A<=A+2
 (2)  B.L<=Rn.L C<=Rn.L PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=B.H:D
 (3)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I97. 0101XXXX1000XXXX (addq.l, subq.l to Rn)
I98. 0101XXXX01001XXX (addq, subq to An)
 (1)  Rm<=F C<=Math1(Rn.L,F) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rn.L<=C D<=[LAST] PREFETCH[LAST]
 (3)  C<=Math2(Rn.H,Rm.H) CCR<=Flags.H
 (4)  Rn.H<=C FETCH F<=IMM A<=PC+2
 End

I99. 0101XXXX0X000XXX (addq.b/w, subq.b/w to Dn)
 (1)  Rm<=F C<=Math1(Rn.L,F) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rn.L<=C D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2 W
 End

I100. 001000011100XXXX (move.l Rn, abs.w)
 (1)  B.L<=Rn.L C<=Rn.L PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=D
 (2)  E,[DATA:A]<=Rn.H C<=Rn.H CCR<=Flags.H A<=A+2
 (3)  [DATA:A]<=B.L FETCH F<=IMM A<=PC+2
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I101. 00X100011100XXXX (move.b/w Rn, abs.w)
A116. 00X1000111XXXXXX (move.b/w to abs.w)
 (1)  B.L<=Rn.L C<=Rn.L PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=D
 (2)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 (3)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (4)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I102. 1X00XXX100000XXX (abcd, sbcd Dn, Dm)
 (1)  B<=Rn.L C<=Math1(Rm.L,Rn.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  C<=Math2(BCD,C) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H A<=B
 (3)  Rm.L<=C FETCH F<=IMM A<=PC+2 W
 End

I103. 0111XXX0XXXXXXXX (moveq)
 (1)  Rm<=F PC<=A C<=F CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I104. 0010XXX10100XXXX (move.l Rn, d(Am))
A122. 0010XXX101XXXXXX (move.l to d(Am))
 (1)  PREFETCH[PROGRAM:A] PC<=A A<=D+Am
 (2)  E,[DATA:A]<=Rn.H C<=Rn.H CCR<=Flags.H A<=A+2
 (3)  [DATA:A].B<=Rn.L C<=Rn.L CCR<=Flags.L A<=PC+2 CHECK
 (4)  PC<=A C<=E D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.H FETCH F<=IMM A<=A+2
 End

I105. X0X1XXX10100XXXX (move.b/w Rn, d(Am))
A114. 00X1XXX101XXXXXX (move.b/w to d(Am))
 (1)  PREFETCH[PROGRAM:A] PC<=A A<=D+Am
 (2)  [DATA:A].B<=Rn.L C<=Rn.L CCR<=Flags.L A<=PC+2 CHECK
 (3)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (4)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I106. X010XXX01100XXXX (move.l Rn, (Am)+)
A120. 0010XXX011XXXXXX (move.l to (Am)+)
 (1)  E,[DATA:Am]<=Rn.H PC<=A A<=Am+2
 (2)  [DATA:A]<=Rn.L C<=Rn.L CCR<=Flags.L A<=A+2 CHECK
 (3)  Am<=A C<=E D<=[PROGRAM:PC] PREFETCH[PROGRAM:PC] CCR<=Flags.H FETCH F<=IMM A<=PC+2
 End

I107. X0X1XXX01100XXXX (move.b/w Rn, (Am)+)
A139. 00X1XXX011XXXXXX (move.b/w to (Am)+)
 (1)  [DATA:Am].B<=Rn.L C<=Rn.L CCR<=Flags.L PC<=A A<=Am+Sz CHECK
 (2)  Am<=A D<=[PROGRAM:PC] PREFETCH[PROGRAM:PC] FETCH F<=IMM A<=PC+2
 End

I108. X010XXX10000XXXX (move.l Rn, -(Am))
A121. 0010XXX100XXXXXX (move.l to -(Am))
 (1)  C<=Rn.L D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=Am-Sz CHECK
 (2)  C<=Rn.H CCR<=Flags.H [DATA:A]<=C A<=A-2
 (3)  Am<=A [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

I109. X0X1XXX10000XXXX (move.b/w Rn, -(Am))
A143. 00X1XXX100XXXXXX (move.b/w to -(Am))
 (1)  C<=Rn.L D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=Am-Sz CHECK
 (2)  Am<=A [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

I110. X010XXX01000XXXX (move.l Rn, (Am))
A109. 0010XXX010XXXXXX (move.l to (Am))
 (1)  E,[DATA:Am]<=Rn.H PC<=A A<=Am+2
 (2)  [DATA:A]<=Rn.L C<=Rn.L CCR<=Flags.L A<=PC CHECK
 (3)  PC<=A C<=E D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.H FETCH F<=IMM A<=A+2
 End

I111. X0X1XXX01000XXXX (move.b/w Rn, (Am))
A111. 00X1XXX010XXXXXX (move.b/w to (Am))
 (1)  [DATA:Am].B<=Rn.L C<=Rn.L CCR<=Flags.L PC<=A A<=Am+Sz CHECK
 (2)  A<=PC+2 CHECK [PROGRAM:PC]
 (3)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I112. X010XXX11000XXXX (move.l Rn, d(Am, Xm))
A123. 0010XXX110XXXXXX (move.l to d(Am, Xm))
 (1)  C<=D.B
 (2)  PC<=A A<=Am+C NEXTI [PROGRAM:A]
 Byte/Word Index:
  (3)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn.L+A
 Long Index:
  (4)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn+A
 (5)  E,[DATA:A]<=Rn.H C<=Rn.H CCR<=Flags.H A<=A+2
 (6)  [DATA:A].B<=Rn.L C<=Rn.L CCR<=Flags.L A<=PC+2 CHECK
 (7)  PC<=A C<=E D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.H FETCH F<=IMM A<=A+2
 End

I113. X0X1XXX11000XXXX (move.b/w Rn, d(Am, Xm))
A115. 00X1XXX110XXXXXX (move.b/w to d(Am, Xm))
 (1)  C<=D.B
 (2)  PC<=A A<=Am+C NEXTI [PROGRAM:A]
 Byte/Word Index:
  (3)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn.L+A
 Long Index:
  (4)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn+A
 (5)  [DATA:A].B<=Rn.L C<=Rn.L CCR<=Flags.L A<=PC+2 CHECK
 (6)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I114. 1011XXX110000XXX (eor.l Dm, Dn)
A94. 0000XXX010000XXX except #95, #93 (eori.l, ori.l, andi.l, addi.l, subi.l to Dn)
 (1)  C<=Math1(Rn.L,Rm.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rn.L<=C D<=[LAST] PREFETCH[LAST]
 (3)  C<=Math2(Rn.H,Rm.H) CCR<=Flags.H
 (4)  Rn.H<=C FETCH F<=IMM A<=PC+2
 End

I115. 1011XXX10X000XXX (eor.b/w Dm, Dn)
A91. 0000XXX00X000XXX except #88, #89, #90 (eori.b/w, ori.b/w, andi.l, addi.b/w, subi.b/w to Dn)
 (1)  C<=Math1(Rn.L,Rm.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rn.L<=C D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2 W
 End

I116. 1X0XXXX01000XXXX (sub.l, add.l Dn, Dm)
I117. 1X01XXX11X000XXX (subx.l, addx.l Dn, Dm)
I118. 1X01XXX11100XXXX (suba.l, adda.l Rn, Am)
A112. 1X0XXXX010XXXXXX (sub.l, add.l to Dm)
A140. 1X01XXX111XXXXXX (subx.l, addx.l to Dm)
 (1)  B<=Rn.L C<=Math1(Rm.L,Rn.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rm.L<=C D<=[LAST] PREFETCH[LAST]
 (3)  C<=Math2(Rm.H,Rn.H) CCR<=Flags.H
 (4)  Rm.H<=C FETCH F<=IMM A<=PC+2
 End

I119. 1X01XXX01100XXXX (suba.b/w, adda.b/w Rn, Am)
A138. 1X01XXX011XXXXXX (suba.b/w, adda.b/w to Am)
 (1)  B<=Rn.L C<=Math1(Rm.L,Rn.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rm.L<=C D<=[LAST] PREFETCH[LAST]
 (3)  C<=Math2(Rm.H,B.H) CCR<=Flags.H
 (4)  Rm.H<=C FETCH F<=IMM A<=PC+2
 End

I120. 1X0XXXX00X00XXXX (sub.b/w, add.b/w Dm, Rn)
I121. 1X01XXX10X000XXX (sub.b/w, add.b/w Dn, Dm)
A137. 1X0XXXX00XXXXXXX (sub.b/w Dm)
 (1)  B<=Rn.L C<=Math1(Rm.L,Rn.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rm.L<=C D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2 W
 End

I122. 0010XXX00X00XXXX (move.l Rn, Rm)
A118. 0010XXX00XXXXXXX (move.l to Rm)
 (1)  B<=Rn PC<=A C<=Rn.L CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  Rm<=B C<=Rn.H D<=[LAST] PREFETCH[LAST] CCR<=Flags.H FETCH F<=IMM
 End

I123. 0011XXX00100XXXX (movea.b/w Rn, Am)
A117. 0011XXX001XXXXXX (movea.b/w to Am)
 (1)  B<=Rn.L PC<=A A<=A+2 CHECK [PROGRAM:A]
 (2)  Rm<=B C<=Rn.H D<=[LAST] PREFETCH[LAST] CCR<=Flags.H FETCH F<=IMM
 End

I124. 00X1XXX00000XXXX (move.b/w Rn, Dm)
A119. 00X1XXX000XXXXXX (move.b/w to Dm)
 (1)  B<=Rn PC<=A C<=Rn.L CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  Rm.L<=C D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2 W
 End

I125. 010001X011000XXX (move Dn, sr)
A128. 010001X011XXXXXX (move to sr)
 (1)  List,F<=Rn.L A<=A-2
 (2)  SR<=F
 (3)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I126. 01001110011101-1 (Error in schematic? Nonsensical)

I127. 0101XXXX11000XXX (scc)
 (1)  PC<=A C<=0 NEXTI [PROGRAM:A]
 Condition false:
  (2)  Rn.L<=C D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2 W
 Condition true:
  (3)  C<=Math1(-1,C) D<=[LAST] PREFETCH[LAST] A<=B
  (4)  Dn.L<=C FETCH F<=IMM A<=PC+2 W
 End

I128. 010010001X111001 (movem to abs.l)
 (1)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (2)  B.H<=D D<=[PROGRAM:A] A<=A+2
 (3)  B.L<=D A<=A+2 [PROGRAM:A]
 (4)  D<=[LAST] PREFETCH[LAST] NEXT PC<=A A<=B NEXTI
 Movem.w:
  (5)  [DATA:A]<=Rm.L NEXT A<=A+2 NEXTI
  Movem.w: Go to (5)
 Movem.l:
  (6)  [DATA:A]<=Rm.H A<=A+2
  (7)  [DATA:A]<=Rm.L NEXT A<=A+2 NEXTI
  Movem.l: Go to (6)
 (8)  A<=PC+2 CHECK [PROGRAM:PC]
 (9)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I129. 010010001X111000 (movem to abs.w)
 (1)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (2)  B<=D A<=A+2 [PROGRAM:A]
 (3)  D<=[LAST] PREFETCH[LAST] NEXT PC<=A A<=B NEXTI
 Movem.w:
  (4)  [DATA:A]<=Rm.L NEXT A<=A+2 NEXTI
  Movem.w: Go to (4)
 Movem.l:
  (5)  [DATA:A]<=Rm.H A<=A+2
  (6)  [DATA:A]<=Rm.L NEXT A<=A+2 NEXTI
  Movem.l: Go to (5)
 (7)  A<=PC+2 CHECK [PROGRAM:PC]
 (8)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I130. 1110XXXX100XXXXX (shift/rotate long immediate)
 (1)  C<=Rn.H PC<=A A<=F CHECK [PROGRAM:A]
 (2)  G<=C C<=Dn.L D<=[LAST] PREFETCH[LAST] CCR<=Flags.L A<=A-Sz NEXTI Cy
 A.Count != 0:
  (3)  C<=Math3(-1,C) CCR<=Flags.L A<=A-Sz NEXTI Cy
  A.Count != 0: Go to (3)
 (4)  Dn.L<=C Rn.H<=G E<=G
 (5)  C<=E CCR<=Flags.H FETCH F<=IMM A<=PC+2
 End

I131. 1110XXXX0X0XXXXX (shift/rotate byte/word immediate)
 (1)  C<=Rn.H PC<=A A<=F CHECK [PROGRAM:A]
 (2)  G<=C C<=Dn.L D<=[LAST] PREFETCH[LAST] CCR<=Flags.L A<=A-Sz NEXTI Cy
 A.Count != 0:
  (3)  C<=Math3(-1,C) CCR<=Flags.L A<=A-Sz NEXTI Cy
  A.Count != 0: Go to (3)
 (4)  Dn.L<=C FETCH F<=IMM A<=PC+2 W
 End

I132. 1110XXXX101XXXXX (shift/rotate long register)
 (1)  C<=Rn.H PC<=A A<=Rm.L CHECK [PROGRAM:A]
 (2)  G<=C C<=Dn.L D<=[LAST] PREFETCH[LAST] CCR<=Flags.L A<=A-Sz NEXTI Cy
 A.Count != 0:
  (3)  C<=Math3(-1,C) CCR<=Flags.L A<=A-Sz NEXTI Cy
  A.Count != 0: Go to (3)
 (4)  Dn.L<=C Rn.H<=G E<=G
 (5)  C<=E CCR<=Flags.H FETCH F<=IMM A<=PC+2
 End

I133. 1110XXXX0X1XXXXX (shift/rotate byte/word register)
 (1)  C<=Rn.H PC<=A A<=Rm.L CHECK [PROGRAM:A]
 (2)  G<=C C<=Dn.L D<=[LAST] PREFETCH[LAST] CCR<=Flags.L A<=A-Sz NEXTI Cy
 A.Count != 0:
  (3)  C<=Math3(-1,C) CCR<=Flags.L A<=A-Sz NEXTI Cy
  A.Count != 0: Go to (3)
 (4)  Dn.L<=C FETCH F<=IMM A<=PC+2 W
 End

I134. 010010001X101XXX (movem to d(An))
 (1)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (2)  B<=D A<=A+2 [PROGRAM:A]
 (3)  PREFETCH[LAST] NEXT PC<=A A<=An+D NEXTI
 Movem.w:
  (4)  [DATA:A]<=Rm.L NEXT A<=A+2 NEXTI
  Movem.w: Go to (4)
 Movem.l:
  (5)  [DATA:A]<=Rm.H A<=A+2
  (6)  [DATA:A]<=Rm.L NEXT A<=A+2 NEXTI
  Movem.l: Go to (5)
 (7)  A<=PC+2 CHECK [PROGRAM:PC]
 (8)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I135. 010010001X010XXX (movem to (An))
 (1)  List,F<=D A<=A+2 [PROGRAM:A]
 (2)  PREFETCH[LAST] NEXT PC<=A A<=An NEXTI
 Movem.w:
  (3)  [DATA:A]<=Rm.L NEXT A<=A+2 NEXTI
  Movem.w: Go to (3)
 Movem.l:
  (4)  [DATA:A]<=Rm.H A<=A+2
  (5)  [DATA:A]<=Rm.L NEXT A<=A+2 NEXTI
  Movem.l: Go to (4)
 (6)  A<=PC+2 CHECK [PROGRAM:PC]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I136. 010010001X110XXX (movem to d(An, Xn))
 (1)  List,F<=D D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+4
 (2)  B.L<=D PC<=A C<=D.B A<=A-2
 (3)  A<=An+C NEXTI [PROGRAM:A]
 Byte/Word Index:
  (4)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn.L+A NEXTI
 Long Index:
  (5)  D<=[LAST] PREFETCH[LAST] NEXT A<=Xn+A NEXTI
 Movem.w:
  (6)  [DATA:A]<=Rm.L NEXT A<=A+2 NEXTI
  Movem.w: Go to (6)
 Movem.l:
  (7)  [DATA:A]<=Rm.H A<=A+2
  (8)  [DATA:A]<=Rm.L NEXT A<=A+2 NEXTI
  Movme.l: Go to (7)
 (9)  A<=PC+2 CHECK [PROGRAM:PC]
 (10)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I137. 0100111001110010 (stop)
 (1)  List,F<=D PC<=A C<=0 FETCH A<=A+2 CHECK
 (2)  PC<=A FETCH SR<=F A<=A-2
 End

I138. 0100000011000XXX (move sr, Dn)
 (1)  F<=SR PC<=A CHECK [PROGRAM:A]
 (2)  Rn.L<=F D<=[LAST] PREFETCH[LAST]
 (3)  FETCH F<=IMM A<=PC+2
 End

I139. 0100111001101XXX (move usp, Dn)
 (1)  B<=Rm BIT#<=Rm.L PC<=A A<=Rn CHECK [PROGRAM:A]
 (2)  Rn<=B D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2
 End

I140. 0100100001000XXX (swap Dn)
 (1)  B.H<=Rn.L E<=Rn.L C<=Rn.H CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rn.H<=B.H An.L<=A.L Dn.L<=C C<=E D<=[LAST] PREFETCH[LAST] CCR<=Flags.H FETCH F<=IMM A<=A+2
 End

I141. 0100111001110000 (reset)
 (1)  List,F<=D PC<=A C<=0 FETCH A<=A+2
 (2)  A<=C-2 CHECK
 (3)  A<=A-2 RESET
 (4)  RESET NEXTI
 A.Count != 0: Go to (3)
 (5)  D<=[PROGRAM:PC] PREFETCH[PROGRAM:PC] FETCH F<=IMM A<=PC+2
 End

I142. 0000XXX010XXXXXX except I147 (eori.l, ori.l, andi.l, subi.l, addi.l)
 (1)  Rm.H<=D D<=[PROGRAM:A] A<=A+2
 (2)  Rm.L<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 Stage2

I143. 0110XXXXXXXXXXXX except I146, I144, I145 (bcc with 8-bit displacement)
 (1)  A<=PC+F NEXTI
 Condition false:
  (2)  FETCH F<=IMM A<=PC+2
 Condition true:
  (3)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I144. 0110XXXX00000000 except I146 (bcc with 16-bit displacement)
 (1)  A<=D+PC NEXTI
 Condition false:
  (2)  FETCH F<=IMM A<=PC+2
  (3)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 Condition true:
  (4)  D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (5)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (6)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I145. 01100001XXXXXXXX except I146 (bsr with 8-bit displacement)
 (1)  B<=PC C<=PC.L A<=Am-4
 (2)  [DATA:A]<=B.H Rm<=A A<=A+2
 (3)  [DATA:A]<=C A<=F+PC
 (4)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (5)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (6)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I146. 0110000100000000 (bsr with 16-bit displacement)
 (1)  B<=A C<=A.L A<=Am-4
 (2)  [DATA:A]<=B.H Rm<=A A<=A+2
 (3)  [DATA:A]<=C A<=D+PC
 (4)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (5)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (6)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

A88. 000011000X000XXX (cmpi.b/w Dn)
 (1)  C<=Math1(Rn.L,Rm.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2
 End

A92. 0000XXX00X111100 (eori, ori, andi to sr)
 (1)  F<=SR A<=PC-2
 (2)  C<=Math1(Dm.L,F)
 (3)  List,F<=C A<=A+2
 (4)  SR<=F
 (5)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (6)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

A95. 0000110010000XXX (cmpi.l Dn)
 (1)  C<=Math1(Rn.L,Rm.L) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  C<=Math2(Rn.H,Rm.H) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H
 (3)  FETCH F<=IMM A<=PC+2
 End

A96. 0000XXX100XXXXXX (btst dynamic immediate)
 (1)  BIT#<=Dm.L Rn.H<=B.H PC<=A W CHECK [PROGRAM:A]
 (2)  E<=Rn.L C<=Rn.L D<=[LAST] PREFETCH[LAST] A<=PC+2 NEXTI
 High byte/word:
  (3)  C<=BIT&Rn.H CCR<=Flags.L FETCH F<=IMM
 Low byte/word:
  (4)  Rn.L<=C C<=BIT&E CCR<=Flags.L FETCH F<=IMM
 End

A124. 00100-1111XXXXXX (Error in schematic)
Last edited by Gigasoft on Tue Feb 16, 2021 3:45 am, edited 4 times in total.

Gigasoft
Very interested
Posts: 95
Joined: Fri Jan 01, 2010 2:24 am

Re: 68K inner workings

Post by Gigasoft » Sun Feb 14, 2021 2:59 am

Part 2:

Code: Select all

B96. 0000XXX100XXXXXX (btst dynamic memory)
B97. 0000100000XXXXXX (btst static memory)
 (1)  PC<=A C<=BIT&D CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B98. 00001000X1XXXXXX (bchg, bset static memory)
B99. 0000XXX1X1XXXXXX (bchg, bset dynamic memory)
 (1)  E<=D PC<=A C<=Math1(BIT,D) D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2 CHECK
 (2)  C<=BIT&E CCR<=Flags.L [DATA:B].B<=C FETCH F<=IMM
 End

B100. 000011000XXXXXXX (cmpi.b/w memory)
 (1)  PC<=A C<=Math1(D,Rm.L) CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B101. 0000XXX00XXXXXXX except #97, #98, #100 (eori.b/w, ori.b/w, andi.b/w, subi.b/w, addi.b/w to memory)
B102. 1XXXXXX10XXXXXXX (sub.b/w, add.b/w to memory)
 (1)  C<=Math1(D,Rm.L) D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=B CHECK
 (2)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B103. 11100XXX11XXXXXX (shift/rotate memory)
 (1)  PC<=A C<=D CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  C<=Math3(-1,C) D<=[LAST] PREFETCH[LAST] CCR<=Flags.L A<=B
 (3)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B104. 0000100010XXXXXX (bclr static memory)
B106. 0000XXX110XXXXXX (bclr dynamic memory)
 (1)  E<=D C<=Math1(BIT,D) F<=SR CHECK [PROGRAM:A]
 (2)  PC<=A C<=Math3(BIT,C) D<=[LAST] PREFETCH[LAST] A<=A+2
 (3)  C<=BIT&E CCR<=Flags.L [DATA:B].B<=C FETCH F<=IMM
 End

B105. 0000110010XXXXXX (cmpi.l memory)
 (1)  PC<=A C<=Math1(D,Rm.L) CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  C<=Math2(G,Rm.H) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H FETCH F<=IMM
 End

B107. 0000XXX010XXXXXX except #104, #105 (eori.l, ori.l, andi.l, subi.l, addi.l to memory)
B131. 1XXXXXX110XXXXXX (eor.l, or.l, and.l, sub.l, add.l to memory)
 (1)  C<=Math1(D,Rm.L) D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=B CHECK
 (2)  C<=Math2(G,Rm.H) CCR<=Flags.H [DATA:A]<=C A<=A-2
 (3)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B108. 0100101010XXXXXX (tst.l memory)
 (1)  PC<=A C<=D CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  C<=E D<=[LAST] PREFETCH[LAST] CCR<=Flags.H FETCH F<=IMM
 End

B109. 0010XXX010XXXXXX (move.l to (Am))
 (1)  [DATA:Am]<=G C<=D CCR<=Flags.L PC<=A A<=Am+2
 (2)  C<=E CCR<=Flags.H [DATA:A]<=C A<=A+2 CHECK
 (3)  A<=PC+2 CHECK [PROGRAM:PC]
 (4)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B110. 01000XX010XXXXXX (negx.l, clr.l, neg.l, not.l memory)
 (1)  C<=Math1(0,D) D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=B CHECK
 (2)  C<=Math2(0,E) CCR<=Flags.H [DATA:B]<=C A<=B-2
 (3)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B111. 00X1XXX010XXXXXX (move.b/w to (Am))
 (1)  [DATA:Am].B<=D C<=D CCR<=Flags.L PC<=A A<=Am+Sz
 (2)  A<=PC+2 CHECK [PROGRAM:PC]
 (3)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B112. 1X0XXXX010XXXXXX (or.l, eor.l, and.l, sub.l, add.l memory)
B140. 1X01XXX111XXXXXX (suba.b/w, adda.b/w memory)
 (1)  B<=D C<=Math1(Rm.L,D) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rm.L<=C C<=Math2(Rm.H,E) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H
 (3)  Rm.H<=C FETCH F<=IMM A<=PC+2
 End

B113. 1011XXX010XXXXXX (cmp.l memory)
B144. 1011XXX111XXXXXX (cmpa.b/w memory)
 (1)  B<=D C<=Math1(Rm.L,D) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  C<=Math2(Rm.H,E) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H
 (3)  FETCH F<=IMM A<=PC+2
 End

B114. 00X1XXX101XXXXXX (move.b/w memory to d(Am))
 (1)  C<=D PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=C+Am
 (2)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 (3)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (4)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B115. 00X1XXX110XXXXXX (move.b/w memory to d(Am, Xm))
 (1)  C<=C.B
 (2)  PC<=A A<=Am+C NEXTI [PROGRAM:A]
 Byte/Word Index:
  (3)  C<=D PREFETCH[LAST] CCR<=Flags.L A<=Xn.L+A
 Long Index:
  (4)  C<=D PREFETCH[LAST] CCR<=Flags.L A<=Xn+A
 (5)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 (6)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B116. 00X1000111XXXXXX (move.b/w memory to abs.w)
 (1)  C<=D PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=C
 (2)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 (3)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (4)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B117. 0011XXX001XXXXXX (movea.b/w memory)
 (1)  Rm<=D PC<=A A<=A+2 CHECK [PROGRAM:A]
 (2)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B119. 00X1XXX000XXXXXX (move.b/w memory to Dm)
 (1)  Rm.L<=D PC<=A C<=D CCR<=Flags.L A<=A+2 W CHECK [PROGRAM:A]
 (2)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B120. 0010XXX011XXXXXX (move.l memory to (Am)+)
 (1)  [DATA:Am]<=G C<=D CCR<=Flags.L PC<=A A<=Am+2
 (2)  C<=E CCR<=Flags.H [DATA:A]<=C A<=A+2 CHECK
 (3)  Am<=A D<=[PROGRAM:PC] PREFETCH[PROGRAM:PC] FETCH F<=IMM A<=PC+2
 End

B121. 0010XXX100XXXXXX (move.l memory to -(Am))
 (1)  C<=D D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=Am-Sz CHECK
 (2)  C<=E CCR<=Flags.H [DATA:A]<=C A<=A-2
 (3)  Am<=A [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B122. 0010XXX101XXXXXX (move.l memory to d(Am))
 (1)  C<=D PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=C+Am
 (2)  B.L<=C [DATA:A]<=G C<=E CCR<=Flags.H A<=A+2
 (3)  [DATA:A]<=B.L FETCH F<=IMM A<=PC+2
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B123. 0010XXX110XXXXXX (move.l memory to d(Am, Xm))
 (1)  C<=C.B
 (2)  PC<=A A<=Am+C NEXTI [PROGRAM:A]
 Byte/Word Index:
  (3)  C<=D PREFETCH[LAST] CCR<=Flags.L A<=Xn.L+A
 Long Index:
  (4)  C<=D PREFETCH[LAST] CCR<=Flags.L A<=Xn+A
 (5)  B.L<=C [DATA:A]<=G C<=E CCR<=Flags.H A<=A+2
 (6)  [DATA:A]<=B.L FETCH F<=IMM A<=PC+2
 (7)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (8)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B124. 001000-111XXXXXX (Error in schematic)

B125. 01000XX00XXXXXXX (negx.b/w, clr.b/w, neg.b/w, not.b/w memory)
 (1)  C<=Math1(0,D) D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=B CHECK
 (2)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B126. 00X1001111XXXXXX (move.b/w memory to abs.l)
 (1)  B.H<=C C<=D D<=[PROGRAM:A] CCR<=Flags.L PC<=A
 (2)  [DATA:B.H:D].B<=C A<=PC+2 CHECK
 (3)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B127. 0100000011XXXXXX (move sr to memory)
 (1)  F<=SR PC<=A CHECK [PROGRAM:A]
 (2)  C<=F D<=[LAST] PREFETCH[LAST] A<=B
 (3)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B128. 010001X011XXXXXX (move memory to sr)
 (1)  List,F<=D A<=A-2
 (2)  SR<=F
 (3)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B129. 0100100000XXXXXX (nbcd memory)
 (1)  C<=Math1(0,D) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  C<=Math2(BCD,C) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H A<=B
 (3)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B130. 010010100XXXXXXX (tst.b/w memory)
 (1)  PC<=A C<=D CCR<=Flags.L A<=A+2 CHECK [PROGRAM:A]
 (2)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B132. 0100101011XXXXXX (tas memory)
 (1)  C<=Math1(D,F) PC<=A A<=B
 (2)  C<=D CCR<=Flags.L [DATA:A].B<=C A<=PC
 (3)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (4)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B133. 0100XXX110XXXXXX (chk memory)
 (1)  E<=Dm.L C<=Math1(D,Dm.L) CCR<=Flags.L A<=A-2
 (2)  PC<=A C<=E CCR<=Flags.L A<=A+2 NEXTI
 Positive, not overflow:
  (3)  NEXTI
 Negative or overflow:
  (4)  F<=SR A<=PC-2
  (5)  C<=PC.L TRAP A<=SSP-2
  (6)  C<=F [DATA:A]<=C A<=A-4
  (7)  SSP<=A C<=PC.H [DATA:A]<=C F<=Vec A<=A+2
  (8)  B<=F C<=E [DATA:A]<=C A<=A-4
  (9)  PC<=B D<=[DATA:B] A<=B+2
  (10)  B.H<=D D<=[DATA:A] A<=A+2
  (11)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
  (12) 
 (13)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (14)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B134. 0101XXXX0XXXXXXX (addq.b/w, subq.b/w to memory)
 (1)  Rm<=F C<=Math1(D,F) D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=B CHECK
 (2)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B135. 0101XXXX10XXXXXX (addq.l, subq.l to memory)
 (1)  Rm<=F C<=Math1(D,F) D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=B CHECK
 (2)  C<=Math2(G,Rm.H) CCR<=Flags.H [DATA:A]<=C A<=A-2
 (3)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B136. 0101XXXX11XXXXXX (scc memory)
 (1)  PC<=A C<=0 NEXTI [PROGRAM:A]
 Condition false:
  (2)  D<=[LAST] PREFETCH[LAST] NEXT PC<=A A<=B
 Condition true:
  (3)  C<=Math1(-1,C) D<=[LAST] PREFETCH[LAST] A<=B
 (4)  [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B137. 1X0XXXX00XXXXXXX (eor.b/w, or.b/w, and.b/w, sub.b/w, add.b/w memory)
 (1)  B<=D C<=Math1(Rm.L,D) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rm.L<=C D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2 W
 End

B138. 1X01XXX011XXXXXX (suba.b/w, adda.b/w memory)
 (1)  B<=D C<=Math1(Rm.L,D) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  Rm.L<=C D<=[LAST] PREFETCH[LAST]
 (3)  C<=Math2(Rm.H,B.H) CCR<=Flags.H
 (4)  Rm.H<=C FETCH F<=IMM A<=PC+2
 End

B139. 00X1XXX011XXXXXX (move.b/w memory to (Am)+)
 (1)  [DATA:Am].B<=D C<=D CCR<=Flags.L PC<=A A<=Am+Sz CHECK
 (2)  Am<=A D<=[PROGRAM:PC] PREFETCH[PROGRAM:PC] FETCH F<=IMM A<=PC+2
 End

B141. 1000XXX011XXXXXX (divu memory)
 (1)  B.H<=D E<=D G<=Dm.L C<=D CCR<=Flags.L PC<=A
 (2)  C<=Math1(Rm.H,E) CCR<=Flags.L NEXTI
 Nonzero:
  (3)  B.L<=None C<=Rm.H CCR<=Flags.L A<=None:F+Sz NEXTI Cy
  Carry:
   (4)  C<=Math3(-1,C) A<=A-Sz NEXTI Cy
   Positive:
    (5)  B.L<=C C<=Math1(C,E) CCR<=Flags.L NEXTI
    A.Count = 0:
     (6)  Rm.H<=C C<=0 NEXTI
     Carry:
      (7)  Rm.H<=B.L E<=C C<=Math3(-1,C) A<=PC+2 CHECK [PROGRAM:PC]
      (8)  Rm.L<=G C<=Math1(G,E) D<=[LAST] PREFETCH[LAST] CCR<=Flags.L FETCH F<=IMM
      End
     Not carry:
      (9)  E<=C C<=Math5(-1,C) A<=PC+2 CHECK [PROGRAM:PC]
      Go to (8)
    A.Count != 0:
     (10)  NEXTI
     Carry:
      (11)  C<=B.L CCR<=Flags.L
      Go to (4)
     Not carry:
      (12)  C<=Math5(-1,C) A<=A-Sz NEXTI Cy
      Positive: Go to (5)
      Negative:
       (13)  B.L<=C C<=Math1(C,E) CCR<=Flags.L NEXTI
       A.Count = 0:
        (14)  Rm.H<=C C<=0
        Go to (9)
       A.Count != 0: Go to (12)
   Negative: Go to (13)
   Go to (8)
  Not carry:
   (15)  A<=PC+2 CHECK [PROGRAM:PC]
   (16)  C<=None|None.B D<=[LAST] PREFETCH[LAST] CCR<=Flags.L FETCH F<=IMM
   End
 Zero:
  (17)  F<=SR A<=PC-2
  (18)  PC<=A C<=A.L TRAP A<=SSP-2
  (19)  C<=F [DATA:A]<=C A<=A-4
  (20)  SSP<=A C<=PC.H [DATA:A]<=C F<=Vec A<=A+2
  (21)  B<=F C<=E [DATA:A]<=C A<=A-4
  (22)  PC<=B D<=[DATA:B] A<=B+2
  (23)  B.H<=D D<=[DATA:A] A<=A+2
  (24)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
  (25) 
  (26)  PC<=A A<=A+2 CHECK [PROGRAM:A]
  (27)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B142. 1000XXX111XXXXXX (divs memory)
 (1)  B.H<=D E<=D G<=Dm.L C<=D CCR<=Flags.L PC<=A
 (2)  C<=Math1(0,E) CCR<=Flags.L NEXTI
 Negative:
  (3)  B.L<=None E<=C C<=Rm.H CCR<=Flags.L A<=None:F+Sz Cy
  (4)  C<=Math1(0,Rm.L) NEXTI
  Positive:
   (5)  C<=Math1(B.L,E) CCR<=Flags.L
  Negative:
   (6)  G<=C C<=Math2(0,Rm.H)
   (7)  B.L<=C C<=Math1(C,E) CCR<=Flags.L
  (8)  C<=B.L CCR<=Flags.L NEXTI
  Carry:
   (9)  C<=Math3(-1,C) A<=A-Sz Cy
   (10)  B.L<=C C<=Math1(C,E) CCR<=Flags.L NEXTI
   A.Count != 0:
    (11)  NEXTI
    Carry:
     (12)  C<=B.L CCR<=Flags.L
     Go to (9)
    Not carry:
     (13)  C<=Math5(-1,C) A<=A-Sz Cy
     Go to (10)
   (14)  NEXTI
   Carry:
    (15)  C<=Math3(-1,C) A<=A-Sz Cy
   Not carry:
    (16)  B.L<=C C<=Math5(-1,C)
   (17)  C<=B.H CCR<=Flags.L
   (18)  E<=G C<=Rm.H CCR<=Flags.L NEXTI
   Positive:
    (19)  B.H<=B.L C<=E CCR<=Flags.L NEXTI
    Positive:
     (20)  B.L<=C C<=C CCR<=Flags.L A<=PC+2 NEXTI [PROGRAM:PC]
     Positive:
      (21)  Rm<=B D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2
      End
     Negative:
      (22)  C<=None|None.B D<=[LAST] PREFETCH[LAST] CCR<=Flags.L FETCH F<=IMM
      End
    Negative:
     (23)  C<=Math1(0,E) CCR<=Flags.L
     (24)  B.L<=C E<=C C<=Math1(0,B.H) NEXTI
     Zero:
      (25)  B.H<=C C<=E CCR<=Flags.L A<=PC+2 CHECK [PROGRAM:PC]
      Go to (21)
     Nonzero:
      (26)  A<=PC+2 CHECK [PROGRAM:PC]
      Go to (22)
   Negative:
    (27)  B.H<=B.L C<=E CCR<=Flags.L NEXTI
    Positive:
     (28)  C<=Math1(0,E) CCR<=Flags.L CHECK
     (29)  B.L<=C C<=C CCR<=Flags.L A<=PC+2 NEXTI [PROGRAM:PC]
     Zero: Go to (21)
     Nonzero: Go to (22)
    Negative:
     (30)  B.L<=C E<=C C<=Math1(0,B.H) NEXTI
     Positive: Go to (25)
     Negative: Go to (26)
  Not carry:
   (31)  A<=PC+2 CHECK [PROGRAM:PC]
   Go to (22)
 Positive:
  (32)  B.L<=None C<=Rm.H CCR<=Flags.L A<=None:F+Sz Cy
  Go to (4)
 Zero:
  (33)  F<=SR A<=PC-2
  (34)  PC<=A C<=A.L TRAP A<=SSP-2
  (35)  C<=F [DATA:A]<=C A<=A-4
  (36)  SSP<=A C<=PC.H [DATA:A]<=C F<=Vec A<=A+2
  (37)  B<=F C<=E [DATA:A]<=C A<=A-4
  (38)  PC<=B D<=[DATA:B] A<=B+2
  (39)  B.H<=D D<=[DATA:A] A<=A+2
  (40)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
  (41) 
  (42)  PC<=A A<=A+2 CHECK [PROGRAM:A]
  (43)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

B143. 00X1XXX100XXXXXX (move.b/w memory to -(Am))
 (1)  C<=D D<=[PROGRAM:A] PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=Am-Sz CHECK
 (2)  Am<=A [DATA:A].B<=C FETCH F<=IMM A<=PC+2
 End

B145. 1011XXX00XXXXXXX (cmp.b/w memory)
 (1)  B<=D C<=Math1(Rm.L,D) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM A<=PC+2
 End

B146. 1011XXX011XXXXXX (cmpa.b/w memory)
 (1)  B<=D C<=Math1(Rm.L,D) CCR<=Flags.L PC<=A CHECK [PROGRAM:A]
 (2)  C<=Math2(Rm.H,B.H) D<=[LAST] PREFETCH[LAST] CCR<=Flags.H
 (3)  FETCH F<=IMM A<=PC+2
 End

B147. 1100XXXX11XXXXXX (muls, mulu memory)
 (1)  B<=A E<=Dm.L G<=D C<=0 CCR<=Flags.L A<=None:F CHECK [PROGRAM:A]
 (2)  Rm.L<=C D<=[LAST] PREFETCH[LAST] NEXTI
 1 unsigned:
  (3)  C<=Math2(C,E) CCR<=Flags.H
 1 signed:
  (4)  C<=Math1(C,E) CCR<=Flags.H
 (5)  PC.L<=B.L C<=Math3(-1,C) CCR<=Flags.H A<=A-Sz NEXTI Cy
 01 signed or 1x unsigned: Go to (3)
 10 signed: Go to (4)
 Neither: Go to (5)
 A. Count = 0:
  (6)  Rm.H<=C PC.H<=B.H Am.L<=B.L Dm.L<=G C<=C CCR<=Flags.H FETCH F<=IMM A<=B+2
  End
The ALU has its own instruction decoder which selects between 13 different sets of 3 functions each, and it can also perform an AND operation, and byte sign extension. When performing shift operations, the ALU is chained with the G register. Usually, the G register contains the high word and the ALU operates on the low word. During divisions and multiplications, it is the opposite.

IC = Internal carry flag, always written
U = undefined
X = X flag
x = ALU flags
p = Shifting flags
|,& = Combine with existing flags
! = Invert flag

ALU operations are as follows:

Code: Select all

DIV
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  0  0  0  -
1: A - B         x  &x x  0  0  !x !x -
2: A - B - IC    x  &x x  0  0  !x !x -
3: (A & B) SHL 1 x  &x x  0  0  p  p  - (ALU <= Shifter)

ADD/ASR/MOVE
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  -  0  -  -
1: A + B         x  &x x  x  x  x  x  x
2: A + B + IC    x  &x x  x  x  x  x  x
3: A & (B LSR 1) x  &x x  0  0  p  p  p

ABCD/ASL
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  -  0  -  -
1: A + B + X     -  -  x  x  x  x  x  x
2: A + B + IC    x  &x x  x  x  |x |x x
3: (A & B) SHL 1 x  &x x  |p |p p  p  p

AND/SWAP/LSL/CLR
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  -  0  -  -
1: A & B         x  &x x  0  0  x  x  -
2: A & B         x  &x x  0  0  x  x  -
3: (A & B) SHL 1 x  &x x  0  0  p  p  p

SUB/NEG/LSR
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  -  0  -  -
1: A - B         x  &x x  x  x  !x !x !x
2: A - B - IC    x  &x x  x  x  !x !x !x
3: A & (B LSR 1) x  &x x  0  0  p  p  p

CMP/CHK
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  0  0  0  -
1: A - B         x  &x x  x  x  !x !x -
2: A - B - IC    x  &x x  x  x  !x !x -
3: A + B + U     x  &x x  0  0  p  p  p

MUL
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  0  0  0  -
1: A - B         x  &x x  x  x  !x !x !x
2: A + B         x  &x x  x  x  x  x  x
3: A & (B LSR 1) x  &x x  0  0  !x !x !x (LessThan >= ALU >= Shifter)

EXT/ROXR
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  -  X  -  -
1: A ^ Ext(B)    x  &x x  0  0  x  x  -
2: A & B         x  &x x  0  0  !x !x -
3: A & (B ROXR 1)x  &x x  0  0  p  p  p

SBCD/NBCD/ROL/LINK
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  -  0  -  -
1: A - B - X     -  -  x  x  x  x  x  x
2: A + B + 1     x  &x x  x  x  !x !x !x
3: (A & B) ROL 1 x  &x x  0  0  p  p  -

SUBX/NEGX/ROR
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  -  0  -  -
1: A - B - X     &x &x x  x  x  x  x  x
2: A - B - IC    x  &x x  x  x  x  x  x
3: A & (B ROR 1) x  &x x  0  0  p  p  -

NOT/ROXL
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  -  X  -  -
1: A - B - 1     x  &x x  x  x  x  x  -
2: A - B - 1     x  &x x  x  x  x  x  -
3: A & (B ROR 1) x  &x x  0  0  p  p  p

ADDX
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x x  0  0  0  0  -
1: A + B + X     &x &x x  x  x  x  x  x
2: A + B + IC    x  &x x  x  x  x  x  x
3: A + B + U     x  &x x  x  x  x  x  x

EOR/BTST/BCHG
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x -  -  0  -  0  -
1: A ^ B         x  &x x  0  0  0  0  -
2: A ^ B         x  &x x  0  0  0  0  -
3: A + B + U     x  &x x  0  0  x  x  x

OR/BCLR/BSET
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x -  -  0  -  0  -
1: A | B         x  &x x  0  0  0  0  -
2: A | B         x  &x x  0  0  0  0  -
3: A ^ B         x  &x x  0  0  0  0  0

TST/TAS/DBCC
Op     Value     ZL ZH N  VL VH CL CH X
|: A | Ext(B)    x  &x x  0  1  0  0  -
&: A & B         x  &x -  -  0  -  0  -
1: A | B         x  &x x  0  0  0  0  -
2: A + B         x  &x x  0  0  x  x  -
3: A + B + U     x  &x x  0  0  x  x  x
Last edited by Gigasoft on Tue Feb 16, 2021 3:46 am, edited 1 time in total.

Gigasoft
Very interested
Posts: 95
Joined: Fri Jan 01, 2010 2:24 am

Re: 68K inner workings

Post by Gigasoft » Tue Feb 16, 2021 3:42 am

Some reconstructed missing instructions, whose microcode addresses do not follow from the schematic. There are, however, columns that look like a possible result from an error in vectorization involving the decoder lines for these instructions.

Code: Select all

I126a. 0100111001110101 (rts)
 (1)  C<=D D<=[DATA:Am].B A<=Am+Sz
 (2)  B.H<=D D<=[DATA:A] A<=A+2
 (3)  Rm<=A PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

I126b. 0100111001110X11 (rtr, rte)
 (1)  C<=D D<=[DATA:Am].B A<=Am+Sz
 (2)  List,F<=D D<=[DATA:A] PREFETCH[DATA:A] A<=A+2
 (3)  B<=D A<=A+2 [DATA:A]
 (4)  B.H<=D Rm<=A D<=[LAST] SR<=F
 (5)  PREFETCH[PROGRAM:B.H:D] A<=B.H:D+2
 (6)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (7)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

A124a. 0010001111XXXXXX (move.l immediate to abs.l) = I95
A124b. 0010000111XXXXXX (move.l immediate to abs.w) = I100

B124a. 0010001111XXXXXX (move.l memory to abs.l):
 (1)  B.L<=D B.H<=C C<=E D<=[PROGRAM:A] PC<=A
 (2)  C<=B.L CCR<=Flags.L [DATA:B.H:D]<=C A<=B.H:D+2
 (3)  C<=E CCR<=Flags.H [DATA:A]<=C A<=PC+2 CHECK
 (4)  List,F<=D PC<=A D<=[PROGRAM:A] PREFETCH[PROGRAM:A] A<=A+2
 (5)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (6)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End
 
B124b. 0010000111XXXXXX (move.l memory to abs.w):
 (1)  C<=D PREFETCH[PROGRAM:A] CCR<=Flags.L PC<=A A<=C
 (2)  B.L<=C [DATA:A]<=G C<=E CCR<=Flags.H A<=A+2
 (3)  [DATA:A]<=B.L FETCH F<=IMM A<=PC+2
 (4)  PC<=A A<=A+2 CHECK [PROGRAM:A]
 (5)  D<=[LAST] PREFETCH[LAST] FETCH F<=IMM
 End

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