SCBR is generated by the VDP so it's probably an input. Interestingly, this signal isn't connected to the 5364 chip in the VA3 at all. It just goes straight from the VDP to the color encoder.
Actually, are you sure this is actually SBCR (connected to VDP pin 50) and not VCLK (connected to VDP pin 49). 7.6MHz makes much more sense if it's the latter and VCLK is connected to the 5364 in the VA3.
Yes, this is my guess as well. Also having SBCR at anything different from PAL/NTSC clocks would break video output anyway.
VCLK is probably an input clock to this chip and is used to drive output signals and internal counters.
It should be MCLK/4 when !HSYNC is not asserted, but it should alternate between MCLK/4 and MCLK/5 (I forget the exact pattern, might be something like 3 clocks of /5 and then 1 of /4 or something like that) when !HSYNC is asserted. Weird that you're not seeing any clock output when !HSYNC is asserted.
It could be that VCLK input is needed for driving EDCLK generation (which is divided from MCLK), which would explain that EDCLK is MCLK/4 for some cycles then MCLK/5, etc... while /HSYNC is low.
It would be interesting to verify is there are any differences regarding EDCLK between MD VA1 and late rmodels since it seems VA1 (and likely VA0) is using an earlier version of 315-5345 chip (see 315-5339 description here:
http://www.tmeeco.eu/SMD/MD1VA1_315-5339.jpg) which does not use VCLK (and neither/SRES, /RAS0, /ZWAIT and /BGACK, which could indicate they are all parts of the same added function)
It's A14 from the perspective of the 68K and A13 from the perspective of the individual RAM chip (or the Z80 in SMS/MarkIII mode). The signals are called IA14/A14 in the official schematics though.
Yes, this is signal was added to force RAM mirroring in MS compatibility mode like with a real Master System. This is required for game compatibility I guess. In MS compatibility mode (/M3 asserted low on cartridge port) , ZA0-ZA15 are connected to VA1-VA16 and RAM chip is accessed (/RAS0 and eventually /OE0 asserted by VDP) when VA16=VA15=1 (since it corresponds to ZA15=ZA14=1) but since VA14 is also connected to RAM chip and can be driven by Z80 (it corresponds to ZA13 and master system games set the stack to $DFF0 generally), it must be forced high to ensure Z80 accesses to $C000-$DFFF mirror accesses to $E000-$FFFF.
/NOE is forced to 0 when /M3 is asserted. Otherwise both /NOE and /EOE follow /OE0. Not affected by any other signal.
My guess would be that in original Mega Drive design, /OE0 was directly connected from VDP to both RAM chips /OE pins but this caused some issue when accessing RAM in MS compatibility mode because VD8-VD15 were driven by the unused RAM chip (maybe some of those signals are used for other purpose in MS compatibility mode, just like VA23 is used to trigger Z80 /NMI), so they added a circuit to generate RAM chips /OE separately.
However, from just looking at the scope output on /BGACK, /ZWAIT and /CAS0, it seems that /BGACK is an output as its driven to 1 and both /ZWAIT and /CAS0 are floating around 0 but not being driven.
Probably you will have different results if you connect VCLK input to a proper clock.
/BGACK can not be an output only since it's driven by the VDP when doing DMA, it's more likely pulled high internally to handle cases where it is floating (when neither Z80 or VDP are masters of 68k bus) as it is used by internal logic.
My guess would be that this signal is used to handle extra RAM refresh to fix some issues discovered after the design of original chips.
We know RAM refresh is handled by VDP (by asserting /OE0 without /RAS0 every xxx VCLK cycles) but it's possible RAM is not refreshed by VDP when /BGACK is low (which would mean someone else is master of the bus) so they needed to add a refresh logic for when /BGACK is low. It could explain also why RAM refresh appears to be twice faster when DMA is executing (there is some post on the forum about this).
As for /CAS0, I'm not sure. In MS compatibility mode, it is connected by PBC to Master System /RD pin and I would have think it's still driven by VDP in MS compatibility mode. Probably it is used to do RAM refresh only when RAM is not accessed as it"s an address strobe for any access (read only or read/write, I'm not sure as I have seen conflicting infos before) outside RAM (/RAS0 and /CAS0 are exclusive).
Otherwise (if not driven by VDP when /M3 is low), it could be generated by this chip and was added to fix compatibility issues with MS cartridge that use the /RD pin.
/ZWAIT is most likely an output and might be needed to delay Z80 RAM access using VCLK input as counter ?