I've been going through the code today and trying to figure things out.
The tech manual says that Name Table entries (addr part) are normally 10-bits wide, but 11-bits wide in Interlaced mode...
http://emu-docs.org/Genesis/sega2f.htm
I've also put comments in the code for the registers now, which makes things much clearer...
Code: Select all
----------------------------------------------------------------
-- REGISTERS
----------------------------------------------------------------
ADDR_STEP <= REG(15); -- Address Auto-increment (8 bits. This number gets added to the RAM access addr after each access).
H40 <= REG(12)(0); -- Horizontal 40-Cell mode (0 = 32-Cell mode, 1 = 40-Cell mode).
-- V30 bit is set in PAL mode.
V30 <= REG(1)(3); -- Bug fix! - Changed to match tech docs / Shaho source (OzOnE).
-- (Was set to Reg 2.)
HSCR <= REG(11)(1 downto 0); -- H Scroll Mode (0 = Full, 1 = Prohibited, 2 = Each 1 Cell scroll, 3 = Each 1 Line scroll).
VSCR <= REG(11)(2); -- V Scroll Mode (0 = Full scroll, 1 = 2-Cell scroll).
-- Scroll sizes used for both Scroll A and Scroll B (I think?) OzOnE.
HSIZE <= REG(16)(1 downto 0); -- H Scroll Size (0 = H 32 Cell, 1 = H 64 Cell, 2 = Prohibited, 3 = H 128 Cell).
VSIZE <= REG(16)(5 downto 4); -- V Scroll Size (0 = V 32 Cell, 1 = V 64 Cell, 2 = Prohibited, 3 = V 128 Cell).
WVP <= REG(18)(4 downto 0); -- Window V Position.
WDOWN <= REG(18)(7); -- Window DOWN / Up (0 = Window is Up from base pos, 1 = Window is DOWN from base pos).
WHP <= REG(17)(4 downto 0); -- Window H Position.
WRIGT <= REG(17)(7); -- Window RIGHT / Left (0 = Window is Left from base pos, 1 = Window is RIGHT from base pos).
BGCOL <= REG(7)(5 downto 0); -- Background Colour.
HIT <= REG(10); -- Horizontal Interrupt - Sets raster on which to trigger an H Int (if H int bit enabled, below).
IE1 <= REG(0)(4); -- Enable H Interrupt (68000 Level 4).
IE0 <= REG(1)(5); -- Enable V Interrupt (68000 Level 6).
DMA <= REG(1)(4); -- Enable DMA ("M1" bit).
IM <= REG(12)(1); -- Interlaced mode bits.
IM2 <= REG(12)(2); -- (0 = Non-interlace, 1 = Interlace, 2 = Prohibited, 3 = Interlace-Double-Resolution).
-- Base addresses
HSCB <= REG(13)(5 downto 0); -- HSCROLL Data Table base address.
NTBB <= REG(4)(2 downto 0); -- Name Table Base address for Scroll B.
NTWB <= REG(3)(5 downto 1); -- Name Table Base address for Window.
NTAB <= REG(2)(5 downto 3); -- Name Table Base address for Scroll A.
SATB <= REG(5)(6 downto 0); -- Sprite Attrib Table Base address.
-- Read-only registers
ODD <= FIELD when IM = '1' else '0';
IN_DMA <= DMA_FILL or DMA_COPY or DMA_VBUS;
STATUS <= "111111" & FIFO_EMPTY & FIFO_FULL & VINT_TG68_PENDING & SOVR & SCOL & ODD & IN_VBL & IN_HBL & IN_DMA & V30;
HV <= HV_VCNT(8 downto 1) & HV_HCNT(8 downto 1) when IM = '0' else -- IM bit is 0 in Non-interlace modes.
HV_VCNT(8 downto 2) & HV_VCNT(9) & HV_HCNT(8 downto 1) when IM = '1'; -- Note: IM bit should be set in both Intelace and Interlace-double-res modes!
@Jorge, does that mean I just halve the name table pointer in Interlace mode (is it only in double-res mode, or whenever Interlace is enabled? ie. IM bit set?).
So, could I just shift the NT pointer bits right by one bit?
I can't quite visualize how the interlaced lines get rendered, or how the NT pointer change addresses the 8x16 cells instead of 8x8?
It's slowly starting to make sense now that I've found the hardware manual though.
@Eke - many thanks for that. I will try to track down the problem now.
I will try getting Reads to work from the real YM chip, but would be nice to fix the timers on the FPGA as well.
It's probably easier if I post the code and you can have a quick look.
It's not too bad now with the registers commented.
Grégory said it's fine for me to post the updated code, but please be aware that this is NOT and official release in any way.
I'm still having weird compilation issues as well, but the code should be OK...
https://mega.co.nz/#!f4w1kToC!XGxcIiWbR ... rOH4c70RcI
This is the version with Shaho's PSG code, but with one YM channel enabled (chan 2). The other channels have been commented out in the gen_fm.vhd file, otherwise the design wouldn't fit on the DE1.
For some strange reason, even if I assign the PSG / FM busses to the Hex displays on the DE1, all music / effects are silent?
It's like Quartus is routing something wrong, and doesn't want to assign to two different things at once? Crazy!
If anyone has had similar issues with VHDL or Quartus before, please let me know.
I mean, I literally just added this...
HEXVALUE(15 downto <= FM_DI(7 downto 0);
HEXVALUE(7 downto 0) <= PSG_DI(7 downto 0);
And it stopped outputting data to the PSG and FM block / YM chip!?
Anyway, it's mostly working atm.
I'm still using the real YM chip, but would be great to get interlace mode working, and fix the Timer issue.
I've added a proper joypad port too, but haven't wired it up yet.
Oh btw, I did add Shaho's gen_io.vhd file to that source as well, so it now routes the inputs for the second joypad port from the top level file.
OzOnE.