Hi Charles and cero,
Thanks to you both for your posts. Sorry for the length of my reply but I want to get everything down in case that helps me get to a solution!
About the TMSS, I'm not even getting that far. When I load the Sonic the Hedgehog ROM onto my SDRAM cart plugged into my Mega Drive 2 and then hit the on button on the Mega Drive, I get a very quick small flash of white bars but then just a black screen.
If I put a retail cartridge into the Mega Drive and turn it on I get the same instant white bars flash (I guess that happens when any device connected to a CRT turns on) but then I get the TMSS "Produced by or under license from Sega Enterprises" and the game boots.
As a note, I have fixed the ROM size calculation on my retail cartridge reader/writer - I suspected that it wasn't using the header to determine ROM size but a manual 'read address near edge of 256KB, 512KB, 1MB, 2MB", etc and see if the data changes, then determine the ROM size that way.
So what I did was hack my CPLD code to mask all SDRAM addresses to a max of 512KB, like this:
Code: Select all
STATE_SDRAM_ReadForMD_ReadWord: begin
sdramAddress <= { 2'b0, mdAddress_sync & 22'h3FFFF };
end
Obviously if I get the rest of the cart working I will program a more intelligent masking algorithm but I'm just trying to get Sonic working for now, and Sonic 1 is 512KB.
Well my suspicions were correct, putting the mask in there made the retail cartridge reader correctly determine the size of the ROM to be 512KB. I can read the ROM written to the SDRAM of my cartridge using this retail cart reader and it is byte for byte a match with the ROM loaded from a retail Sonic 1 cartridge read from the same retail cart reader.
So just to be clear, I put a genuine Sonic retail cart into the cart reader, and read that ROM to a file, 512KB.
Then I use that file and send it to my cartridge - it writes it to the SDRAM onboard.
Then I plug my cartridge into the reader and read that ROM, 512KB to a file.
The files are byte for byte the same.
So thanks Charles for your offer to check the header for me, but the whole ROM is readable now and is correct so that answers that question.
What is interesting is that if I involve the CE0 signal at all in my CPLD code, the retail reader fails to get any correct data off my cart.
It only works if I only use CAS0. With CE0, the reader says it is an unknown cartridge with no name, 0MB of size and 0KB of SRAM size.
There are 3 places in my code where I can use CAS0 and/or CE0: (and as a note, mdPresence_sync is simply 3.3V for when the cart is plugged into a running Mega Drive, 0V for when it is not plugged into a running Mega Drive):
1) Output Enable/Disable the data transceiver for 5V <-> 3.3V translation. Output disable puts the output of the transceiver to be high Z.
Code is:
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assign mdDataDisable = ~mdPresence_sync | mdReadCAS0_sync;
If I involve CE0 at all the retail cart reader fails.
Eg:
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assign mdDataDisable = ~mdPresence_sync | mdReadCAS0_sync | mdCartRangeCE_0_sync;
And
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assign mdDataDisable = ~mdPresence_sync | mdCartRangeCE_0_sync;
Fails.
2)
The second place is in the main state loop, to see if the Mega Drive is requesting a read. This works on the retail reader:
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STATE_CPLD_Idle: begin
if (mdPresence_sync & ~mdReadCAS0_sync) begin
// we need to read data for the MD
cpld_state_next = STATE_SDRAM_ReadForMD_WaitUntilReady;
end
Again, CE0 breaks it. I would think it would need to be this:
Code: Select all
STATE_CPLD_Idle: begin
if (mdPresence_sync & ~mdReadCAS0_sync & ~mdCartRangeCE_0_sync) begin
// we need to read data for the MD
cpld_state_next = STATE_SDRAM_ReadForMD_WaitUntilReady;
end
But that breaks it.
This fails too:
Code: Select all
STATE_CPLD_Idle: begin
if (mdPresence_sync & ~mdCartRangeCE_0_sync) begin
// we need to read data for the MD
cpld_state_next = STATE_SDRAM_ReadForMD_WaitUntilReady;
end
3)
The last spot is to determine the finish of a read:
Code: Select all
STATE_SDRAM_ReadForMD_WaitForReadToFinish: begin
cpld_state_next = (~mdPresence_sync | mdReadCAS0_sync) ? STATE_CPLD_Idle : STATE_SDRAM_ReadForMD_WaitForReadToFinish;
end
Again CE0 stuffs things up.
Maybe this is impacting the Mega Drive too? Sadly any combination of using CE0 and not doesn't work on the Mega Drive either. Without any measurement tools I don't know for sure what is happening either.
I thought, maybe there is something faulty with the CE0 line to the CPLD? Perhaps it isn't connected or there is a solder bridge somewhere along the line stuffing things up?
So I tested the CE0 line alongside all adjacent PCB lines as well, in case there is a bridge somewhere impacting the line, but CE0 functions fine - I can set it to 1 or 0 and all adjacent lines too and they are all functioning independently and correctly...
My other thought is that it is just not getting the data to the Mega Drive fast enough - when I first designed and built this PCB I never knew that CPLDs/FPGAs without PLLs would halve incoming clock lines that are output to other ICs - so my CPLD running at 100MHz is actually running the SDRAM at 50MHz.
My SAM4S micro disables DAC sound output if running higher than 100MHz but can run up to 120MHz if DAC output is not needed, so as a test I put the clock up to 120MHz and tightened up the SDRAM timings to the absolute fastest they can be while still returning reliable data.
Of course it still doesn't work on the Mega Drive, but it is still possible that it still isn't fast enough - the SDRAM I have can run up to 133MHz, but I am currently nowhere near that, at 60MHz.
So, unless a new idea comes to me I'm at the point now where I have to choose from 2 options:
1) Bite the bullet and redesign the PCB around SRAM rather than SDRAM, purchase the parts and solder up another board, or:
2) Make a simple PCB that sits between the Mega Drive and a cartridge plugged in that exposes test points for each address, control and data line, and also purchase a logic analyzer to measure what is happening.
With option 2, there is no guarantee that I will be able to solve what is wrong, but I will at least see what is happening, hopefully?
With option 1, it will cost me time to redesign and then time to solder everything again. But there is the chance that it will "just work", saving the cost of purchasing a logic analyzer - I can't find any affordable 32-channel ones. There are some 16 channel ones that could work...
But I wonder why involving the CE0 line at all breaks reading? Anyway thanks to all in advance for any ideas.