FPGA version
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The reason is simple: I don't have any of it. Beside, as I know the TA chipset most accurate clone to original. For example, this TA-04 was replaced by me more than 15 years ago and it still works (burned out arbiter was the reason to change this superclone to onechip MD2 clone):
Anyway, it is better that system was divided into units and testing that units separately is much easier than whole system. You always can assemble those parts into one unit, right?
Anyway, it is better that system was divided into units and testing that units separately is much easier than whole system. You always can assemble those parts into one unit, right?
HAve you guys heard about retro VGS (http://www.retrovgs.com) ?
It's an ARM Cortex 8 (single core, 1GHz) coupled with a 49k EL FPGA.
It's an ARM Cortex 8 (single core, 1GHz) coupled with a 49k EL FPGA.
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We don't need yet another emulator. We want a simulator.ob1 wrote:HAve you guys heard about retro VGS (http://www.retrovgs.com) ?
It's an ARM Cortex 8 (single core, 1GHz) coupled with a 49k EL FPGA.
Of course, of course, I know.
I just wanted to drop the specs.
I was thinking about Kaneda line :
Not emulated.
Just FPGA-simulated.
Sorry if off-topic.
I just wanted to drop the specs.
I was thinking about Kaneda line :
In this "Retro VGS", in what I thought was related, the ARM would be idle, while the FPGA would be the actual Genesis.... i'll like to know if a FPGA (or a SoC) version of Genny is possible ? ...
Not emulated.
Just FPGA-simulated.
Sorry if off-topic.
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Re: FPGA version
Good works.
It Could be interessting.
It à clone of what chip ?
It Could be interessting.
It à clone of what chip ?
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Re: FPGA version
Ok, our team almost done reverse engineering MD ASICs with it's decap. Some of team members was made a hardware level emulator and even FPGA one. Now my turn to finish this project. Finally I done with this:
This is Megadrive that rebuild on custom PCB with possibility to replace the ASICs. I'm gonna recreate the ASICs in CPLD/FPGA and try it in this PCB. There is RAM underneath the ASICs modules.
I found the 1Mx8 5V SRAM chips, so this model able to use 2MB of RAM (from $E00000 through $FFFFFF), but in compatibility purpose it can be reduced to standard 64KB with mirroring. Also I use one half of 32KB chip on the Z80 side. So there avaiable 16KB from $0000 through $3FFF but also can be reduced to standard 8KB with mirroring. VDP mode pin was isolated from region register input at I/O, so able to set all 4 regions on 50Hz or 60Hz VDP mode.
Almost 6 years passed since I posted here pictures of ASICs modules (links to those pictures are dead now) and almost 10 years since I started this project. Now I hope I can finish it, lol.
This is Megadrive that rebuild on custom PCB with possibility to replace the ASICs. I'm gonna recreate the ASICs in CPLD/FPGA and try it in this PCB. There is RAM underneath the ASICs modules.
I found the 1Mx8 5V SRAM chips, so this model able to use 2MB of RAM (from $E00000 through $FFFFFF), but in compatibility purpose it can be reduced to standard 64KB with mirroring. Also I use one half of 32KB chip on the Z80 side. So there avaiable 16KB from $0000 through $3FFF but also can be reduced to standard 8KB with mirroring. VDP mode pin was isolated from region register input at I/O, so able to set all 4 regions on 50Hz or 60Hz VDP mode.
Almost 6 years passed since I posted here pictures of ASICs modules (links to those pictures are dead now) and almost 10 years since I started this project. Now I hope I can finish it, lol.
Re: FPGA version
Hope you finish. It will be great!HardWareMan wrote: ↑Wed Aug 23, 2023 5:29 pmOk, our team almost done reverse engineering MD ASICs with it's decap. Some of team members was made a hardware level emulator and even FPGA one. Now my turn to finish this project. Finally I done with this:
This is Megadrive that rebuild on custom PCB with possibility to replace the ASICs. I'm gonna recreate the ASICs in CPLD/FPGA and try it in this PCB. There is RAM underneath the ASICs modules.
I found the 1Mx8 5V SRAM chips, so this model able to use 2MB of RAM (from $E00000 through $FFFFFF), but in compatibility purpose it can be reduced to standard 64KB with mirroring. Also I use one half of 32KB chip on the Z80 side. So there avaiable 16KB from $0000 through $3FFF but also can be reduced to standard 8KB with mirroring. VDP mode pin was isolated from region register input at I/O, so able to set all 4 regions on 50Hz or 60Hz VDP mode.
Almost 6 years passed since I posted here pictures of ASICs modules (links to those pictures are dead now) and almost 10 years since I started this project. Now I hope I can finish it, lol.
We had mega sg fpga but not sure if you can use their work.
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Re: FPGA version
What a beauty, super impressive! Hope you can cross that finish line!