Service manuals of various Sega machines !

For hardware talk only (please avoid ROM dumper stuff)
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Post by Nemesis » Thu Mar 07, 2013 1:25 am

So which bits define if EDCK is an input or output?
I can confirm from hardware tests, setting bit 7 (RS0) uses the EDCLK input to drive the dot clock, while bit 0 (RS1) switches the digital operation of the chip between H32 and H40 mode. If RS0 is not set, the dot clock is MCLK/5 if RS1 is clear, and MCLK/4 if it is set.

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Post by Eke » Mon Mar 18, 2013 11:38 pm

Nemesis wrote:
EDCK can input twice the pixel clock or output it. It's an input on the Genesis and driven by the bus arbiter chip which alternates between two frequencies in H40 mode. (Why? More sprite drawing time?) I haven't checked how it's used on System 18/C2 yet.
EDCLK alternates between frequencies in order to keep the sync rate within specifications for a PAL/NTSC video signal. In a H32 display, we have 684 dot clock ticks per line, with an internal MCLK/5 divider, which gives us 3420 MCLK cycles per line. When running in H40 mode without EDCLK enabled, you get 840 dot clock ticks per line, with an internal MCLK/4 clock divider. This gives us 3360 MCLK cycles per line, which is too fast for PAL/NTSC displays. The varying clock rate provided by the EDCLK signal generator inserts slower clock cycles during the horizontal blanking regions, where stretched pixels don't matter, because it's all black anyway. There are 60 extra pixel clock cycles added, which increases the MCLK count per line from 3360 to 3420, exactly the same as in H32 mode, and exactly what's needed to generate a video signal at the correct rate in PAL/NTSC mode. If the output display could handle the faster sync rate, this wouldn't be required.
So to be clear, this means that the VDP does not really use MCLK input to sync internal processing but Dot Clock (or more exactly a clock running at twice the pixel output rate) and that what determines a line (i.e the period of horizontal events such as HSYNC, HBLANK flag, HINT, ...) is not a fixed number of MCLK cycles but instead Internal/External Clock counter, right ?

As a consequence, there are less MCLK cycles per line, i.e shorter lines and, by extention, faster framerate when the external "dot" clock input is disabled in H40 mode (or even faster when it is enabled in H32 mode btw) ?

Another thing I noted is that, in H40 mode, disabling HSYNC output through reg $C should in theory produce the exact same result as disabling EDCLK input since, in both cases, the clock will be fixed to MCLK/4.

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