FPGA version

[HardWareMan]

ASIC chips are ready. With handy for probing pins.


I visited the idea: I can experience them out of MD environment. I can make testbench for TA-04 and TA-05. TA-06 too complex for this.

[Charles MacDonald]

I visited the idea: I can experience them out of MD environment. I can make testbench for TA-04 and TA-05. TA-06 too complex for this.

Very nice! Is there a reason why you are looking at the clone chips instead of the originals? Do the clone parts have some interesting or undocumented functions?

[HardWareMan]

The reason is simple: I don't have any of it. Beside, as I know the TA chipset most accurate clone to original. For example, this TA-04 was replaced by me more than 15 years ago and it still works (burned out arbiter was the reason to change this superclone to onechip MD2 clone):

Anyway, it is better that system was divided into units and testing that units separately is much easier than whole system. You always can assemble those parts into one unit, right?

[ob1]

HAve you guys heard about retro VGS (http://www.retrovgs.com) ?
It's an ARM Cortex 8 (single core, 1GHz) coupled with a 49k EL FPGA.

[HardWareMan]

HAve you guys heard about retro VGS (http://www.retrovgs.com) ?
It's an ARM Cortex 8 (single core, 1GHz) coupled with a 49k EL FPGA.

We don't need yet another emulator. We want a simulator.

[ob1]

Of course, of course, I know.
I just wanted to drop the specs.
I was thinking about Kaneda line :

... i'll like to know if a FPGA (or a SoC) version of Genny is possible ? ...

In this "Retro VGS", in what I thought was related, the ARM would be idle, while the FPGA would be the actual Genesis.
Not emulated.
Just FPGA-simulated.

Sorry if off-topic.

[HardWareMan]

Some update.

Need to allocate some time to build working DIY prototype.

[bastien]

Good works.
It Could be interessting.
It à clone of what chip ?

[HardWareMan]

Ok, our team almost done reverse engineering MD ASICs with it's decap. Some of team members was made a hardware level emulator and even FPGA one. Now my turn to finish this project. Finally I done with this:

This is Megadrive that rebuild on custom PCB with possibility to replace the ASICs. I'm gonna recreate the ASICs in CPLD/FPGA and try it in this PCB. There is RAM underneath the ASICs modules.

I found the 1Mx8 5V SRAM chips, so this model able to use 2MB of RAM (from $E00000 through $FFFFFF), but in compatibility purpose it can be reduced to standard 64KB with mirroring. Also I use one half of 32KB chip on the Z80 side. So there avaiable 16KB from $0000 through $3FFF but also can be reduced to standard 8KB with mirroring. VDP mode pin was isolated from region register input at I/O, so able to set all 4 regions on 50Hz or 60Hz VDP mode.

Almost 6 years passed since I posted here pictures of ASICs modules (links to those pictures are dead now) and almost 10 years since I started this project. Now I hope I can finish it, lol.

[danibus]

Ok, our team almost done reverse engineering MD ASICs with it's decap. Some of team members was made a hardware level emulator and even FPGA one. Now my turn to finish this project. Finally I done with this:

This is Megadrive that rebuild on custom PCB with possibility to replace the ASICs. I'm gonna recreate the ASICs in CPLD/FPGA and try it in this PCB. There is RAM underneath the ASICs modules.

I found the 1Mx8 5V SRAM chips, so this model able to use 2MB of RAM (from $E00000 through $FFFFFF), but in compatibility purpose it can be reduced to standard 64KB with mirroring. Also I use one half of 32KB chip on the Z80 side. So there avaiable 16KB from $0000 through $3FFF but also can be reduced to standard 8KB with mirroring. VDP mode pin was isolated from region register input at I/O, so able to set all 4 regions on 50Hz or 60Hz VDP mode.

Almost 6 years passed since I posted here pictures of ASICs modules (links to those pictures are dead now) and almost 10 years since I started this project. Now I hope I can finish it, lol.

Hope you finish. It will be great!
We had mega sg fpga but not sure if you can use their work.

[HardWareMan]

We had mega sg fpga but not sure if you can use their work.

I'll use only our decap project as source. I don't want to use any other one's.