SpritesMind.Net

Think of it this way :

VDP and CPU are two runners on a track, the track has the length of one frame and both of them start at the same time.
VDP does different things depending on what distance it has reached on the track and there are two major sections on the track for it :
*Active part - where ...

In general you do not count Active lines as part of your budget since that is where your game logic runs and in general games do not try to update VRAM in that time but do their logic, wait for Passive scan to start and then start the necessary transfers. So that 237 tiles is the absolute maximum ...

Theoretical maximums in each resolution :
Number of tiles that can be transferred per frame :
+---------+---------------------------+---------------------------+
| | 50Hz | 60Hz |
| +-------------+-------------+-------------+-------------+
| | V224 | V240 | V224 | V240 ...

Yes, both fields of a frame are different so the game is effectively 60FPS. The game doesn't have to wait for both fields to finish drawing before starting the next frame, if it did it would have 30FPS. It is like many PS2 and Dreamcast games that run in interlaced mode but are not necessarily ...

One thing is that the write itself happens at the end of instruction so the delay really starts then and what happens next depends on what comes after. In the end I gave up trying to optimize access speeds and use IX/IY with YMPORT in them permanently, since I don't use them for anything else due to ...

I remember needing a larger than normal delay on key on/off registers when I made my sound driver many years ago, the envelope thing you mention is because the 4bits react differently and sometimes one or more won't do same as others and this can dramatically alter the sound. I also remember getting ...

I would do it to my machines just beacuse I don't have or are unlikely to ever gonna have the RAM cart, those extra 24KB will be most welcome lol

Z80 bus request and reset come from bus chip, using the single data line that is connected to it. Z80 banker also is done by that chip, one bit at a time.

Version register with its many bits comes from the IO chip, and !FDC (MCD presence) and region signals also connect to it.

IO chip has all ...

I think I made a typo and meant to write CXA output instead. Signal levels are near 1Vpp for full while there. It was so long ago so I am not totally sure anymore.

MD VDP RGB DAC output is roughly linear when unloaded indeed, but it is quite high impedance and the loading from the divider will ...

It is driven by 315-5308/5364/5402/5433 and it should be response to FCx pins which also connect to these chips. I don't know any further details though...

*is excited about future*

There is only enough fill rate to cover all of the screen once while using all of the CPU power, due to all the wait states on VRAM access. If you want 60FPS you need to limit amount of stuff that gets drawn, both in area and definitely in overdraw. It is faster to check what has to be drawn and ...

Cartslot is slave only with no means to do bus mastering (it cannot initiate writes to the console, only receive them) so you'll need software help. One way is to hijack frame interrupt, do your thing in it and then run the original handler, but it might break timing sensitive games.

CRAM is a physical array of 64 x 9 bits on the silicon, the unused bits in the data port are simply not connected to the actual memory at least as far as writes are concerned. These unused bits can be anything, they simply are ignored when writes are done. For reads I am unsure what will happen, are ...

A TV often does what is referred to as the overscan, which means that only some part of the full image gets shown on the physical screen. There is no direct pixel mapping going on and because of this a game is not supposed to put anything in the edges of the screen since they are simply not ...