SpritesMind.Net

Jorge Nuno wrote:HardWareMan VDP pin 118

Oh, you're right. My bad.

Well I see the pin is CAS0 on the VDP, but on cart and expansion slot diagrams around the place it seems to be listed as OE. Maybe I'll randomly switch between the two and everyone will have to guess what I'm on about. Here, I'll put it closer to you. http://savepic.ru/13550680m.gif http://savepic....

Yes, it is bus metastability. Since M68K itself can't do that after AS asserting (@design), so this is chipset related problem. Oh, deja vu, is we already discussed it before? Anyway, yes, there is a problem. Since SRAM or ROM can handle with this by that fact that those metastabilities ends before ...

Although I don't know the whole inside SM but I totally agree with you. Same thing happens with me but without having my own forum - I realized long time ago that I can't handle it because sufficient of time. I'm will not make any game or tool because I'm hardware guy. I'm ready to share what I know...

In theory you could do even better than that if there's enough spare room in the FPGA. 68K bus snooping is theoretically enough to mirror the VDP state into the UMDK's RAM. Of course, you would probably want to fix the DMA issues first. That is real thoughts. Most of DMA can be snooped since it use...

Yes, via VDP by M68K CPU way. All I were said previously is UMDK can everything that those devkit does and even more. It is all up to software and FPGA configuration part.

This is my dream kit: https://www.youtube.com/watch?v=A9zQueGP4iI&index=3&list=PLJAZP-TLMPj4JnSB3XAe2k6zO11jhZ6qq I don't know its full capabilities, or whether it's able to read VRAM (probably not), but it's a simple slot-in-and-play solution that's not unlike UMDK. If one of these ever hits eBay ...

It is dynamic load. Because this sample is more likely nMOS (or pMOS) and not CMOS. And second one (with only two elements) is pure CMOS. Here.

I do not understand, hasn't anyone looked at the CPU die shots yet? Basic die shots. Then, Quietust has made a great contribution by isolating the metal traces . Olivier Galibert was able to make use of this layer image, with a few corrections, to produce a full transistor-level schematic of the 680...

Hi and welcome! I am almost certain that these zig-zags are ESD protection structures. These are compulsory protection circuits that must be placed next to the pads of a silicon die. http://savepic.su/1699689.png A lot of time is passed. Now I sure that analog output have only one transistor that ca...

Thank you!

Thank you!

Fileden is died. Who saved those test?

This one? Thank you, I'll try it. But maybe it is time to make some kind set for hardware testing? Maybe we should collect already available ones and make some new one? And place it in special part of Nemesis's site, where anyone can find them.

Thank you for your reply! I'll glad any available test ROM. Indeed, in most cases user must keep an eye by tests. And this is correct. And I hope we make some complex test for it, include some crazy thing like 512 color screen by Oerg866.