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Finally i correct it!
The vdp did not raise cpu v-int for higan core ...
Now sonic is running great with this new core

After adding log trace the problem seems to be the v-int not catched with higan core : traces with musashi 68k : PC = 0x000018A8 PC = 0x000018AA PC = 0x000018AC V-Int! PC = 0x000018B0 Write Addr : 0x00FFFDF6, data : 0xFFF62A -> 0x0000FF1F PC = 0x000018B4 Write Addr : 0x00FFFDF6, data : 0xFFF62A -> 0...

I'm actually implementing higan 68k core in my emulator and i would need help in understanding the code of sonic rom. My emulator actually loop at this place : 0029AC TST.b $FFFFF62A.w 0029B0 BNE.b *+$FA => 0029AC With other 68k core (musashi, c68k ...) everything works ok. Edit : if found this in a...

So in my comprehension : - The VDP lower the interrupt line - When receive IACK from cpu the vdp raise interrupt line This is correct? So if VDP lower interrupt line and raise it before the CPU go in interrupt process the interrupt could be ignored (so pending interrupt == interrupt line in low stat...

I have a question about vdp interrupt processing.
How long the vdp assert interrupt line for Horizontal and Vertical Interrupt?

What could be the reference document in 2021 for 68k timings?
I'l trying to write a 68k core and need a good documentation to implement correct timings.

The cart can't stop the hardware in the console from responding, so it is generally not proper to respond to a read from an address that the console already does. If you want to be compatible with the Sega CD and 32X, you also need to avoid the address ranges they use. The Teradrive additionally us...

thanks for the reply.
So technically the system plugged into the cartridge port could reply to a read/write event adressed to a vdp for example (instead of the vdp himself)?

I have a question about how the genesis component work.

If i don't a misunderstanding a genesis cardridge has his internal adress decoder.
All 24 pins of the adress bus is connected to a cartridge and the cartridge can be mapped to all 68k Memory Space
=> This is correct?

Thanks for reply.

Hello, I saw that somes asian megadrive (new) are selled since few years on internet : https://assets.catawiki.nl/assets/2018/9/20/8/8/8/8882c744-bd73-445b-8e20-ac8933d0d5cf.jpg Does someone know how the region jumpers are configured inside (JP1/2/3/4)? PAL ON? NTSC OFF? ENGLISH OFF? JAPAN ON? Some ...

Thanks for your answers guys. It make sens.

Hello everybody.
I'm asking myself why there is not much game using 8x16 Interlace Mode?
Why developper were using 320x240 mode instead of high resolution mode available on the system (320*480)?

Miquel wrote: ↑

Wed Dec 11, 2019 4:20 pm

No word access: Z80 memory space can only be accessed by the 68k in byte address mode, and that has to mean something.

Does that mean that accessing Z80 space in word mode (UDS and LDS selected) does not have any effects?

Another question about accessing Z80 space from 68K side : From what i understand : - If UDS selected byte will be read at even adress from Z80 bus (addr + 0) and will be returned at upper byte from 68K Bus (D15-D8) - If LDS selected byte will be read at even adress from Z80 bus (addr + 1) and will ...