SpritesMind.Net

I forgot control channel. Here is power up: http://savepic.ru/14634000m.png Little bit closer at reset: http://savepic.ru/14614544.png http://savepic.ru/14634003m.png http://savepic.ru/14662674m.png Shortest nIRQ period is 6.334 ms. http://savepic.ru/14674965m.png The rest periods seems to be multip...

Same here (no audio disk -> audio disk load -> audio disc play): http://savepic.ru/14651418m.png A little bit closer while playing: http://savepic.ru/14623744m.png SCOR period: 1/75 sec. SCOR pulse is right one WFCK clock period. EXCK/SBSO active only when WFCK is low and they push only 8 bits at on...

First approach: http://savepic.ru/14642189.png BCLK = 16MHz / 8. Yes, audio bit clock is 2.1168MHz (16.9344 / 8). 2 116 800 Hz / 48 = 44 100 Hz. Audio CD loading and then playback it: http://savepic.ru/14635020m.png Note that some data is break thru to the DAC, but Mute not allow them to output. I t...

I think it doesn't matter which level of TL/TH you will keep after periph access routine. Most important is switch it to default right before new periph access. Some doubts I have with 6-button joypat. It is have timeout to fall back to LRUD from XYZM. But I don't know, will it work with TL/TH = 0 o...

I'm on my way to connect my logic analyzer to CD drive connector: http://savepic.ru/14632184.png 1 - CDCK (D-->H) CD mechanism control communication clock 2 - D/M (D-->H) Mute, output '0' for playback and '1' for mute 3 - nIRQ (D-->H) Interrupt request 4 - nRES (D<--H) Reset the CD hardware 5 - HOCK...

The drive ribbon wire has these signals:

Did it enough for you?

I must make some handy remote pins because MD1 sits above MCD1 and all PCBs are located under MD1 and MD1 apply some force to EXT connector without detent on the opposite end.

I have MD1 and I can make some records for you.

Every frame of 98 contains not only subchannel data but left and rigth channel samples. I don't remember how much but I guess 6 of each. 44100 / 75 / 98 = 6. 6 * 2 * 2 = 24 bytes.

KanedaFr wrote:Sorry but your first post was a mistery, like..."yes 12...and so ?"

Quite round integer after division, isn't it? I just was want to show this fact. The rest you should have guessed yourself. In fact, there tons of frequencies that pretty multiples to each other. With integer multiplier.

Again: 384 / 2 / 16 = 12. Because 2 channels with 16bit in each. 12x oversampling for one bit Delta-Sigma DAC.

KanedaFr wrote:

TmEE co.(TM) wrote:the 16MHz is 16.934400MHz, which is CDDA bitclock.

I don't understand where this value come from....

16 934 400 / 44 100 / 2 / 16 = 12.

The bus buffers I'm also using another part because I don't trust those 5<->3.3V bidirectional converters. I'm stepping down the 5V signals to 3.3V, but not the other way around. You totally right. There was another project with FC stuff and bidirectional automatic shifters created a big headache. ...

It is a one of possible variant.

Also it has no VD12-VD15. But it provide higher addresses and CE0. Also, it provides MRES and M3. So, basic signals it takes from EXT port, higher addresses and CE0 via this cartrige (that's why 244s need for) and able to MRES (more powerfull than VRES!) and M3. Simple and clever I think.

As I said before, leave discussion and create separate topic for pure checked info only.