SpritesMind.Net

About TMSS I think I'd need to see the entire cartridge "rom" (the fake one baked in to the CPLD) that you're using to answer that. Can you provide a binary dump of the first 256 bytes of the ROM data that you're presenting to the 68K so we can see what it's doing -- like using your cart dumper with ...

I'd guess it's just combinatorial logic but I'd agree that we should get a definitive answer in case it isn't. When I have some free time I'll see if I can test this and let you know.

The last time I looked at this I didn't see any delays added by the hardware. As soon as the interrupt acknowledge cycle ends and AS goes high, then VPA is no longer asserted.

In theory this cycle lasts until it is terminated by VPA, BERR, or DTACK so it could be longer than four clocks but I've ...

The hardware asserts VPA for the duration of the interrupt acknowledge cycle when AS is low and FC1, FC0 are high. See figure 5-10 and 5-11 here (note "IACK CYCLE" in the right half of 5-11) in the manual to see what the timing looks like.

https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf ...

It looks like the GENDEV environment variable isn't set up correctly. In the docs they mention this is needed as a first step (see "Build some sample code")

https://github.com/kubilus1/gendev/blob/master/doc/FreeBSD.md

When you run vscode and make a new terminal it may not be importing the ...

You can still store graphics data in $800000-$9FFFFF if you'd like, you just can't transfer it to the VDP using DMA. Instead you can write 68000 code to transfer the data to the VDP.

If you test it let us know how it works. I think nobody's tried it before, so your results will be interesting.

The ROM3-CE# signal is correct though IC5B doesn't need input A=A23, as A23 is already checked by IC5A, thus when IC5B is decoding A23 is always low.

DTACK# can be the same as your ROM3-CE#, but you can run it through a 74HC1G125 buffer like this to make it open drain:

Input A : Ground
Output ...

TMSS isn't too bad to deal with, it just takes a little more complexity on your end:

1. Your ROM should contain the ASCII text "SEGA" at offset 0x100. (e.g. the CPLD outputs that hardcoded data when reading that memory range)

2. If your diagnostic software needs to write to the VDP, it has to ...

I had a similar kind of experience on a past project and it was helpful to reduce the complexity and just try a simple test case: ignore the SDRAM entirely and output fixed ROM data to run a small program that is only a few words long so it can fit within the CPLD. For example something like:


dc ...

Unfortunately it doesn't speed anything up, the access time during V-Blank is the same as when the screen is turned off.

However you can get more time to do DMA transfers by "letterboxing" the display, where you turn off V-Blank early (say line 200) and then back on late (say line 8 of the next ...

I've seen an issue on some flashcarts and my own dev hardware where there are graphical glitches in this game, during the 7 Force battle when you fight the cat robot thing. It's happened with several different Genesis consoles. Here's how it should look:

https://youtu.be/AaSsBtFD4Xc?t=182

Now what ...

Wow, great job! Nice to have a very technical post to start the new year. :)

About the sprite Y read parts, any idea why it goes up to 15 and not 7 given that there's eight possible sprites per scanline? Or is this a side effect of having to read data in some wider width? (say 16 bits at at time ...

Mask of Destiny, good catch! I've edited my post for clarity.

unlicensed EA games (Budokan, etc.) use H40 mode with the wrong combination of RS1,RS0 set,
How does that even work, that should result in an invalid TV signal.

For one of the combinations of bits yep, it's a scrambled mess, for the ...

Bart did a good write-up on some poorly documented/undocumented aspects of the 68000 too:
https://emu-docs.org/CPU%2068k/68knotes.txt

Other quirks include:

MOVEM reading one address past the source location:
http://gendev.spritesmind.net/forum/viewtopic.php?f=13&t=2010&p=25882

CLR to memory ...

When doing DMA from the 68K address space to VRAM, what happens when the Z80 tries to read banked RAM memory during a long transfer?

I'd assume the Z80 is halted until DMA is over, but I think this would affect sample playback. Is there a priority system where the Z80 can always complete an access ...