Search found 881 matches

by Eke
Thu Jun 02, 2022 8:28 pm
Forum: Video Display Processor
Topic: SMS and SMS mode output levels
Replies: 4
Views: 8757

Re: SMS and SMS mode output levels

I think I made a typo and meant to write CXA output instead. Signal levels are near 1Vpp for full while there. It was so long ago so I am not totally sure anymore. 1Vpp for full white should be at the CXA input according to its datasheet with output being 1.4Vpp for full white still according to da...
by Eke
Thu May 26, 2022 2:56 pm
Forum: Video Display Processor
Topic: SMS and SMS mode output levels
Replies: 4
Views: 8757

Re: SMS and SMS mode output levels

SMS2 : mV, ratio, RGB 0, 0.000, 0 364, 0.350, 89 720, 0.684, 174 1052, 1.000, 255 I was recently trying to figure how to simulate accurate RGB levels of MD1/MD2, MS1 and MS2 RGB models (that were afaik only sold in France) and was wondering about these measured voltages (that correspond to 315-5246...
by Eke
Sun Feb 27, 2022 9:07 am
Forum: Mega/SegaCD
Topic: mcd-verificator (CD core accuracy tests)
Replies: 26
Views: 18945

Re: mcd-verificator (CD core accuracy tests)

Another particularity I recently noticed is that the X'Eye (and likely Wondermega M2) was using 32KB RAM chip (LC33832) with the CDC (LC89513) instead of 16KB in all other Mega-CD models.
by Eke
Sun Feb 27, 2022 8:59 am
Forum: Mega/SegaCD
Topic: Popful Mail
Replies: 16
Views: 17285

Re: Popful Mail

Fuuuuuu... the bugs in that Radical Rex code, and that just in the initial loading routine. Really surprised it runs in any emulator at all. Seems like a frickin' miracle! I know this thread is getting old (and its original author is no more among us sadly) but I recently looked again into this gam...
by Eke
Sat May 15, 2021 11:35 am
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 21159

Re: VDP Status Register

HV counters are not affected by display or interrupts being disabled.
by Eke
Fri May 14, 2021 12:43 pm
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 21159

Re: VDP Status Register

VBLANK flag is forced to 1 whenever the display is disabled/blanked (through VDP register $01 bit 6).
by Eke
Sat Apr 03, 2021 11:46 am
Forum: Megadrive/Genesis
Topic: Question on Golden Axe II
Replies: 4
Views: 3830

Re: Question on Golden Axe II

That's only the 2nd part (ignoring invalid command values on data port writes).

Looking at Higan sourcecode, the error is here:
https://github.com/higan-emu/higan/blob ... o.cpp#L154

io.command[1:0] and io.address[13:0] should also be updated in case of register write
by Eke
Sat Apr 03, 2021 7:37 am
Forum: Megadrive/Genesis
Topic: Question on Golden Axe II
Replies: 4
Views: 3830

Re: Question on Golden Axe II

From memory, this game attempts to write to VRAM after setting the CTRL port for a register write, without setting the address and control registers in between. The solution is to still update the address (lower 14 bits) and code (lower 2 bits) registers when a VDP register write occurs, and ignore ...
by Eke
Fri Mar 19, 2021 1:17 pm
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 21159

Re: VDP Status Register

For what it's worth, I finally got access back to my flashcart and verified the game has notable slowddown on real hardware as well.
Also confirmed that HBLANK flag is still set/cleared normally during VBLANK.
by Eke
Sun Mar 07, 2021 6:10 pm
Forum: Video Display Processor
Topic: VDP VRAM access timing
Replies: 40
Views: 46314

Re: VDP VRAM access timing

Yes, as described in linked topic, active display corresponds to the 256 or 320 active pixels wide area.
by Eke
Sun Mar 07, 2021 12:45 pm
Forum: Mega/SegaCD
Topic: Popful Mail
Replies: 16
Views: 17285

Re: Popful Mail

Well, i know that it does some quite risky synchronization at some points as it locks in emulators unless you carefully lockstep the two cpus but I wasn't aware of any other bugs... All I know is that, when intro is started, a dma occurs to load the sprite table from word-ram but, for some unknown r...
by Eke
Sun Mar 07, 2021 11:58 am
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 21159

Re: VDP Status Register

It is possible this game suffers from slowdown on real hardware too, I can't really tell without testing it.
by Eke
Sun Mar 07, 2021 11:27 am
Forum: Video Display Processor
Topic: VDP VRAM access timing
Replies: 40
Views: 46314

Re: VDP VRAM access timing

According to Nemesis intial post If the cells in layer A and B are perfectly aligned to the screen, so that every cell is entirely visible, these additional reads are still performed, but the results are not used. so the column -1 is always being fetched, even when xcroll & 15 = 0 and the pixel out ...
by Eke
Sat Mar 06, 2021 9:47 am
Forum: Mega/SegaCD
Topic: Popful Mail
Replies: 16
Views: 17285

Re: Popful Mail

Excellent :!:

Now next challenge: let's find out why sprites are invisible in all existing Sega CD emulators during the intro of Radical Rex. This one has been puzzling me for quite some time now (sorry to hijack thread :oops: )
by Eke
Fri Mar 05, 2021 9:38 am
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 21159

Re: VDP Status Register

Sorry to resurrect this old topic but I was wondering if anyone tested if the HBLANK flag (bit 2) was still set normally during VBLANK ? I could not find any info about this but maybe it was already confirmed somewhere ? The reason I ask is that an user reported the game "Double Dragon II" having so...