Search found 885 matches

by Eke
Sat Apr 20, 2024 7:01 pm
Forum: Mega/SegaCD
Topic: Popful Mail
Replies: 17
Views: 366312

Re: Popful Mail

FYI, this long standing issue was finally fixed thanks to the help of irixxxx (developer of a Picodrive fork) who successfuly debuggued the root cause and found the solution : a delay is needed when receiving a CD read command while reading is already in progress to allow at least one additional sec...
by Eke
Tue Aug 08, 2023 8:52 pm
Forum: Mega/SegaCD
Topic: SEGA CD Mode 1
Replies: 57
Views: 367647

Re: SEGA CD Mode 1

Unfortunately, Bizhawk is using a quite old version of Genesis Plus GX so it's probably missing a lot of bugfixes and added features, including automatic Mode 1 support.
by Eke
Sun Aug 06, 2023 9:14 pm
Forum: Announcement
Topic: Nuked MD - decap-based cycle-accurate Mega Drive emulator (software & FPGA)
Replies: 8
Views: 82732

Re: Nuked MD - decap-based cycle-accurate Mega Drive emulator (software & FPGA)

That's impressive... and an unvaluable source of information. Thanks for your work :!:
by Eke
Sun Aug 06, 2023 8:56 pm
Forum: Mega/SegaCD
Topic: SEGA CD Mode 1
Replies: 57
Views: 367647

Re: SEGA CD Mode 1

I think Genesis Plus GX also supports Mode 1 boot these days, but I've personally had trouble figuring out how to get it running. Hi, You only need to have a .cue file with same basename as the ROM file you load, in same directory, and Sega CD Mode 1 should automatically be enabled. Alternatively, ...
by Eke
Thu Jun 02, 2022 8:28 pm
Forum: Video Display Processor
Topic: SMS and SMS mode output levels
Replies: 4
Views: 84427

Re: SMS and SMS mode output levels

I think I made a typo and meant to write CXA output instead. Signal levels are near 1Vpp for full while there. It was so long ago so I am not totally sure anymore. 1Vpp for full white should be at the CXA input according to its datasheet with output being 1.4Vpp for full white still according to da...
by Eke
Thu May 26, 2022 2:56 pm
Forum: Video Display Processor
Topic: SMS and SMS mode output levels
Replies: 4
Views: 84427

Re: SMS and SMS mode output levels

SMS2 : mV, ratio, RGB 0, 0.000, 0 364, 0.350, 89 720, 0.684, 174 1052, 1.000, 255 I was recently trying to figure how to simulate accurate RGB levels of MD1/MD2, MS1 and MS2 RGB models (that were afaik only sold in France) and was wondering about these measured voltages (that correspond to 315-5246...
by Eke
Sun Feb 27, 2022 9:07 am
Forum: Mega/SegaCD
Topic: mcd-verificator (CD core accuracy tests)
Replies: 26
Views: 192599

Re: mcd-verificator (CD core accuracy tests)

Another particularity I recently noticed is that the X'Eye (and likely Wondermega M2) was using 32KB RAM chip (LC33832) with the CDC (LC89513) instead of 16KB in all other Mega-CD models.
by Eke
Sun Feb 27, 2022 8:59 am
Forum: Mega/SegaCD
Topic: Popful Mail
Replies: 17
Views: 366312

Re: Popful Mail

Fuuuuuu... the bugs in that Radical Rex code, and that just in the initial loading routine. Really surprised it runs in any emulator at all. Seems like a frickin' miracle! I know this thread is getting old (and its original author is no more among us sadly) but I recently looked again into this gam...
by Eke
Sat May 15, 2021 11:35 am
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 199173

Re: VDP Status Register

HV counters are not affected by display or interrupts being disabled.
by Eke
Fri May 14, 2021 12:43 pm
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 199173

Re: VDP Status Register

VBLANK flag is forced to 1 whenever the display is disabled/blanked (through VDP register $01 bit 6).
by Eke
Sat Apr 03, 2021 11:46 am
Forum: Megadrive/Genesis
Topic: Question on Golden Axe II
Replies: 4
Views: 114697

Re: Question on Golden Axe II

That's only the 2nd part (ignoring invalid command values on data port writes).

Looking at Higan sourcecode, the error is here:
https://github.com/higan-emu/higan/blob ... o.cpp#L154

io.command[1:0] and io.address[13:0] should also be updated in case of register write
by Eke
Sat Apr 03, 2021 7:37 am
Forum: Megadrive/Genesis
Topic: Question on Golden Axe II
Replies: 4
Views: 114697

Re: Question on Golden Axe II

From memory, this game attempts to write to VRAM after setting the CTRL port for a register write, without setting the address and control registers in between. The solution is to still update the address (lower 14 bits) and code (lower 2 bits) registers when a VDP register write occurs, and ignore ...
by Eke
Fri Mar 19, 2021 1:17 pm
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 199173

Re: VDP Status Register

For what it's worth, I finally got access back to my flashcart and verified the game has notable slowddown on real hardware as well.
Also confirmed that HBLANK flag is still set/cleared normally during VBLANK.
by Eke
Sun Mar 07, 2021 6:10 pm
Forum: Video Display Processor
Topic: VDP VRAM access timing
Replies: 40
Views: 136094

Re: VDP VRAM access timing

Yes, as described in linked topic, active display corresponds to the 256 or 320 active pixels wide area.
by Eke
Sun Mar 07, 2021 12:45 pm
Forum: Mega/SegaCD
Topic: Popful Mail
Replies: 17
Views: 366312

Re: Popful Mail

Well, i know that it does some quite risky synchronization at some points as it locks in emulators unless you carefully lockstep the two cpus but I wasn't aware of any other bugs... All I know is that, when intro is started, a dma occurs to load the sprite table from word-ram but, for some unknown r...