Search found 877 matches

by Eke
Sat May 15, 2021 11:35 am
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 13827

Re: VDP Status Register

HV counters are not affected by display or interrupts being disabled.
by Eke
Fri May 14, 2021 12:43 pm
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 13827

Re: VDP Status Register

VBLANK flag is forced to 1 whenever the display is disabled/blanked (through VDP register $01 bit 6).
by Eke
Sat Apr 03, 2021 11:46 am
Forum: Megadrive/Genesis
Topic: Question on Golden Axe II
Replies: 4
Views: 1136

Re: Question on Golden Axe II

That's only the 2nd part (ignoring invalid command values on data port writes).

Looking at Higan sourcecode, the error is here:
https://github.com/higan-emu/higan/blob ... o.cpp#L154

io.command[1:0] and io.address[13:0] should also be updated in case of register write
by Eke
Sat Apr 03, 2021 7:37 am
Forum: Megadrive/Genesis
Topic: Question on Golden Axe II
Replies: 4
Views: 1136

Re: Question on Golden Axe II

From memory, this game attempts to write to VRAM after setting the CTRL port for a register write, without setting the address and control registers in between. The solution is to still update the address (lower 14 bits) and code (lower 2 bits) registers when a VDP register write occurs, and ignore ...
by Eke
Fri Mar 19, 2021 1:17 pm
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 13827

Re: VDP Status Register

For what it's worth, I finally got access back to my flashcart and verified the game has notable slowddown on real hardware as well.
Also confirmed that HBLANK flag is still set/cleared normally during VBLANK.
by Eke
Sun Mar 07, 2021 6:10 pm
Forum: Video Display Processor
Topic: VDP VRAM access timing
Replies: 40
Views: 35534

Re: VDP VRAM access timing

Yes, as described in linked topic, active display corresponds to the 256 or 320 active pixels wide area.
by Eke
Sun Mar 07, 2021 12:45 pm
Forum: Mega/SegaCD
Topic: Popful Mail
Replies: 14
Views: 9549

Re: Popful Mail

Well, i know that it does some quite risky synchronization at some points as it locks in emulators unless you carefully lockstep the two cpus but I wasn't aware of any other bugs... All I know is that, when intro is started, a dma occurs to load the sprite table from word-ram but, for some unknown r...
by Eke
Sun Mar 07, 2021 11:58 am
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 13827

Re: VDP Status Register

It is possible this game suffers from slowdown on real hardware too, I can't really tell without testing it.
by Eke
Sun Mar 07, 2021 11:27 am
Forum: Video Display Processor
Topic: VDP VRAM access timing
Replies: 40
Views: 35534

Re: VDP VRAM access timing

According to Nemesis intial post If the cells in layer A and B are perfectly aligned to the screen, so that every cell is entirely visible, these additional reads are still performed, but the results are not used. so the column -1 is always being fetched, even when xcroll & 15 = 0 and the pixel out ...
by Eke
Sat Mar 06, 2021 9:47 am
Forum: Mega/SegaCD
Topic: Popful Mail
Replies: 14
Views: 9549

Re: Popful Mail

Excellent :!:

Now next challenge: let's find out why sprites are invisible in all existing Sega CD emulators during the intro of Radical Rex. This one has been puzzling me for quite some time now (sorry to hijack thread :oops: )
by Eke
Fri Mar 05, 2021 9:38 am
Forum: Video Display Processor
Topic: VDP Status Register
Replies: 28
Views: 13827

Re: VDP Status Register

Sorry to resurrect this old topic but I was wondering if anyone tested if the HBLANK flag (bit 2) was still set normally during VBLANK ? I could not find any info about this but maybe it was already confirmed somewhere ? The reason I ask is that an user reported the game "Double Dragon II" having so...
by Eke
Fri Mar 05, 2021 9:15 am
Forum: Video Display Processor
Topic: Megadrive video timings
Replies: 123
Views: 78655

Re: Megadrive video timings

Eke if you read this post i don't see very good how you emulate DMA trigger in middle of instruction in genesis plus. When 68k write the first word what happen in vdp code? You execute the vdp until the DMA finish (render all the line necessary) and then switch back to 68k core to execute second wo...
by Eke
Wed Feb 24, 2021 12:43 pm
Forum: Megadrive/Genesis
Topic: Problem Expanding Super Monaco GP
Replies: 8
Views: 1620

Re: Problem Expanding Super Monaco GP

My bet is that you are triggering an address error exception (which is not emulated in Kega Fusion) because some of the pointers you changed now points to a misaligned address, which would cause the CPU to crash on real hardware (and most recent emulators). You have to make sure any data you are add...
by Eke
Thu Jul 23, 2020 8:18 pm
Forum: Sound
Topic: Sega CD Mode 1 support functions for SGDK
Replies: 25
Views: 15933

Re: Sega CD Mode 1 support functions for SGDK

It is suppose to work with Genesis plus gx, but i can not find any guide for that, so any help is welcome Sorry, I didn't see this post earlier but it's indeed not well documented. It's quite simple to activate Mega CD mode 1 though (I call it "cartridge boot" mode): just put the cue file and assoc...
by Eke
Tue Jul 21, 2020 10:48 am
Forum: Mega/SegaCD
Topic: mcd-verificator (CD core accuracy tests)
Replies: 24
Views: 10979

Re: mcd-verificator (CD core accuracy tests)

I don't think the problem with MCD emulation on flashcarts with 32x is caused by /DTACK since /DTACK is asserted by the console itself when accessing Mega CD registers (in 0xA120xx range). I believe the problem is due to 32X not connecting all address lines to cartridge, which makes it impossible to...