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is that seeking has two consequences for CDD status. While doing some research on seeking, I found that the duration depend of distance (between current pos and wanted pos), perhaps it's what you call "not ready status" ? It was already on my "warning" list because of that. I see it's more sensible...

main page updated with all I know/understand, be free to fix and confirm data By main page, you mean this one , right? One thing that I found a little confusing is that you talk a lot about the CDC, but from the description it sounds like you're talking about the MCU that's part of the CDD in Sega'...

On the CXD2500AQ datasheet, it's written The contents of the subcode interface can be externally read in two ways. The Game Processor get subcodes using the first way : P-W through SBSO, EXCK based. It make sense since MCD support CD+G and so needs more than only subcode Q. The MCE/Game Processor u...

so if I raise SCOR, put anything I want on the 2 first S0S1 bits of the Q subchannel, here we go ? So S0/S1 never get output on SUBQ. Looking at the CXD2500BQ datasheet, it looks like the DSP does Q channel error detection and only outputs the 80 data bits of the Q subchannel (the other 16-bits of ...

We know the 14bits version of the S0 S1 bytes are SYNC0 ( 00100000000001 ) and SYNC1 ( 00000000010010 ) BUT, and this is my problem, I'm absolutely unable to find the 8 bits version I need. why ? because they are reserved patterns (data can't use them, only sync) and so you can't find them on the 2...

Since I can't get interrupts from the PC side, I can't wait for Vblank (as far as I know) to do VGA register writes, so there are artifacts. Looking at the WD90C10 documentation, it looks like you can read the vertical retrace status from bit 3 of IO port $3DA (or $3BA if $3CC/$3C2 bit 0 is 0, but ...

So if there is any more information, test code, annotated disassembly etc that you guys could share, I'd be most grateful. So I actually figured out a bit more since I originally wrote this post. Here are the registers with an updated description 1160: XXXXXXXX Selects an 8 KiB page from the extra ...

Hello, I'm facing a problem, the SGDK flash-save sample doesn't work with Blastem, does it supports SRAM saves ? I just tested Sonic 3 and it works, but it is FRAM. I'll contact Doragasu to know more about its plugin saveman. Cheers Edit: ok I misunderstood, saveman.h is not FRAM save, I gonna use ...

I was able to run it on my Model 2 via my MED v1, but it did crash eventually. Neat demo!

I've been working on Sega Pico and Yamaha Copera (a Pico enhanced with some additional audio hardware) emulation recently. I figured it would be good to write up my findings. I'd like to start by thanking notaz for their existing Pico document, superctr for providing an archive of some Sega Pico sou...

There's some documentation of the format here. It sounds like the audio is uncompressed in the native PCM format of the Ricoh chip (sign-magnitude) so replacing it should be pretty straightforward. I don't think there are any off the shelf tools to do so though

FWIW, BlastEm nightly builds also have Mode 1 support these days and might run on a slightly less beefy machine. My CD compatibility is currently a fair bit worse at the moment, though I do much better on mcd-verficator. I think Genesis Plus GX also supports Mode 1 boot these days, but I've personal...

- Is the problem I see just something that is related to the Exodus emulator? I didn't encounter it yet on my Mega Drive model 2, or with other emulators. But maybe it does happen on other mega drive or genesis models and Exodus is just a better emulator than others? In general, if something doesn'...

I have already corrected the code (disabling VBL IRQ was unnecessary), but I wonder why it works on emulators (fusion, exodus, kgen) and not on the console. EDIT... Eh ... I already know what is wrong, instead of writing $ 8114 under mode set register #2 I wrote $ 8120 ... :( So you inadvertently s...

The only real restriction is that setting VDP registers also messes with the configured address/destination for writes/reads/DMA. The other thing to keep in mind is that disabling vertical interrupts this way is that it doesn't clear the interrupt pending state. So let's say you had vertical interru...