Page 1 of 1
FIFO
Posted: Sun Feb 04, 2007 7:56 pm
by ob1
Hi you all.
Still on 32x dev' ;)
I'm looking at the FIFO. First of all, is it usable ? Or is it DREQ only ?
The 68k writes to A1 5112h, and the SH2s read 2000 4012h. But is it a stack, a heap or anything ? And if so, how big is it ?
I mean, if the 68k want to put several datas, does it have to wait the SH2s to grab the data in the FIFO for each value ?
Re: FIFO
Posted: Sun Feb 04, 2007 10:42 pm
by Stef
ob1 wrote:Hi you all.
Still on 32x dev'
I'm looking at the FIFO. First of all, is it usable ? Or is it DREQ only ?
The 68k writes to A1 5112h, and the SH2s read 2000 4012h. But is it a stack, a heap or anything ? And if so, how big is it ?
I mean, if the 68k want to put several datas, does it have to wait the SH2s to grab the data in the FIFO for each value ?
I don't remember exactly how it work but you have a software method (the 68k keep writing the FIFO reg during the SH2 keep reading it) and a hardware one (main SH2 DMA unit is used)... it's a bit complexe to use them. Why don't use the communication buffer ? It's still the best and easiest way to exchange quickly small amount of data.
Re: FIFO
Posted: Tue Feb 06, 2007 6:01 am
by ob1
Stef wrote:It's still the best and easiest way to exchange quickly small amount of data.
For small data, I agree. But what about bigger data ? Anyway, I think I understand how the FIFO runs. The DMA remais a bit unclear for now, but it's going to change soon ;)
Anyway, how big is the FIFO ? I've only found this assumption in cpu_sh2.c :
So, 4 16-bit words long ?
Posted: Tue Feb 06, 2007 7:28 am
by Stef
Exactly, the FIFO is 4 words (16 bits) length
And for big exchange, it's the fastest way...
Posted: Tue Feb 06, 2007 8:21 am
by ob1
OK, so I've done a little 32X ROM, with just the 68k running. Here's the code :
Code: Select all
start68k:
move.l #$A15106,a0 ; DREQ Control Register
move.l #$A15112,a1 ; FIFO Register
move.w #4,(a0) ; CPU write (68k writes data in FIFO)
moveq #0,d1
whileFIFONotFull:
move.w (a0),d0
andi.w #$80,d0
bne FIFOFull
move.w d1,(a1)
addq #1,d1
bra whileFIFONotFull
FIFOFull:
bra FIFOFull
end68k:
or, for you Cish guys,
Code: Select all
int main() {
int * FIFO_CTRL_REG = (int *) 0xA15106;
int * FIFO_REG = (int *) 0xA15112;
int FIFO_FULL = 0x80;
int i=0;
while (!(*FIFO_CTRL_REG & FIFO_FULL)) {
*FIFO_REG = i;
i++;
}
}
and guess what ... d1 = 8 !!!
So, FIFO is 8 16-bit words long ?
Posted: Tue Feb 06, 2007 10:39 am
by Stef
Strange, in Gens i implemented it as a 4 words buffer :-/ based on the documented i got at this time. .. anyway, the hardware gave you the true
Posted: Tue Feb 06, 2007 10:44 am
by ob1
Posted: Tue Feb 06, 2007 12:56 pm
by Stef
Gens can be wrong, it should not really impact on compatibility.
Did you tried your bit of code on Gens ?
Posted: Tue Feb 06, 2007 1:14 pm
by ob1
I've tried it on Gens.
Posted: Tue Feb 06, 2007 3:44 pm
by Stef
and Gens reply 8 ? lol
I've to admit i don't understand the point anyway i can test the rom on real hardware if you want
but but... i just realized :
memset (_32X_FIFO_A, 0, 4 * 2);
You get that info from the Gens sources right ?
Posted: Tue Feb 06, 2007 4:17 pm
by ob1
Yeah, I got it from the sources.
4*2 = 8, ok.
But 8 what ? 8 bytes ? Or 8 16-bit words ?
Seeing 4*2, I'm thinking about 4 2-bytes (16-bit) words.
Or is it really 8 16-bit words ?