68k patents

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flamewing
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68k patents

Post by flamewing » Sat Oct 13, 2018 10:28 am

I have been taking a dive in the 68k patents recently, trying to find if there was a version with a more recent version of the microcode. Additionally, I was also looking to see if any other patents might have the microcode from page 164 of US4325121, which is cut off, or maybe some additional information on how corf is computed, and so on. In the process, I tracked a few patents that have some interesting information which do not seem to be available elsewhere. Sources searched were US, European, and Japanese patents; but for Japanese patents, I only really bothered with one patent because you can't download a PDF from the JPO website.

Here is the full list of 68k patents I found, with links.
Anyway, still need to go through everything in these patents, but they sadly don't seem to give nearly as much information as I hoped. Still, there are some new circuits that may be of use in understanding parts of the 68k.

ijor
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Re: 68k patents

Post by ijor » Fri Nov 30, 2018 2:51 am

flamewing wrote:
Sat Oct 13, 2018 10:28 am
I have been taking a dive in the 68k patents recently, trying to find if there was a version with a more recent version of the microcode.
I'm no aware about any patents with the microcode updated with DBcc and the actual exception processing. All the patents seem to be before prototyping. But the actual microcode, except those two and that most addresses were changed, is almost identical at the one on the patents.
Meaning that the bus cycle finishes before the address error triggers. Searching a bit, this has been observed in Atari STE in the Atari forums (see here). Note that the cycle counts given prove the information of the patent, but they are not truly representative of the 68k; ...
I'm not exactly sure what you mean by "the address error triggers". If you mean before exception logic microcode starts, then yes, of course, there is no other way that it could be done. This is also true for bus error.

But the address error cycle really never fully starts. AS and RW is asserted, but (UL)DS is not.

The cycle counting at the patent is wrong. It is wrong for almost all exceptions because the microcode has an additional microblock. If it matched any test performed at the ST it was by pure chance. For the reasons you mentioned, the exception timing on the ST is different than the nominal one.
http://github.com/ijor/fx68k (68000 cycle accurate FPGA core)

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Re: 68k patents

Post by flamewing » Mon Dec 03, 2018 8:21 am

ijor wrote: I'm no aware about any patents with the microcode updated with DBcc and the actual exception processing.
Yes, which is what I wanted to prove for sure.
ijor wrote: I'm not exactly sure what you mean by "the address error triggers". If you mean before exception logic microcode starts, then yes, of course, there is no other way that it could be done. This is also true for bus error.
At least according to the patent describing bus error, this is not true: it describes the bus error as aborting the current bus cycle instead of waiting for it to "finish". Then, there is the retry logic, and if the retry fails, the retried bus cycle is also aborted before the bus error signal is asserted. Meaning that an address error could, at least in theory, use a similar logic to abort the bus cycle, in this case before it even starts.
ijor wrote: But the address error cycle really never fully starts. AS and RW is asserted, but (UL)DS is not.
There are two different things being called "bus cycle" here, which are important to distinguish: the external bus cycle, and the internal bus cycle. The external bus cycle is all the set of signals being sent by the 68k to the external bus. The internal bus cycle is the state machine that drives this. During an address error, the internal bus cycle proceeds normally, as if the 68k were doing a perfectly valid bus access; however, the external bus cycle is effectively killed by the address error signal, as you describe. A bus error, on the other hand, stops the internal bus cycle cold as soon as it is detected.
ijor wrote: The cycle counting at the patent is wrong. It is wrong for almost all exceptions because the microcode has an additional microblock. If it matched any test performed at the STE it was by pure chance.
Sorry, I should have been clearer: I was not comparing the microcode timing from the patents with those exception tables. I was comparing with timings obtained from Galibert's analysis, plus the added bus cycle time, to the STE tables.

Edit: actually, I now remember: I wasn't even comparing actual cycle counts with the table; I was just confirming that the full effective address time was added to the exception processing time in the case of address error. Still, I should have been clearer.

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Re: 68k patents

Post by ijor » Wed Dec 05, 2018 2:41 am

flamewing wrote:
Mon Dec 03, 2018 8:21 am
ijor wrote: I'm not exactly sure what you mean by "the address error triggers". If you mean before exception logic microcode starts, then yes, of course, there is no other way that it could be done. This is also true for bus error.
At least according to the patent describing bus error, this is not true: it describes the bus error as aborting the current bus cycle instead of waiting for it to "finish". Then, there is the retry logic, and if the retry fails, the retried bus cycle is also aborted before the bus error signal is asserted. Meaning that an address error could, at least in theory, use a similar logic to abort the bus cycle, in this case before it even starts.
The patent is not exact. But regardless, this doesn't contradict what I said. The bus cycle on both bus and address error ends well before the exception microcode takes control.
There are two different things being called "bus cycle" here, which are important to distinguish: the external bus cycle, and the internal bus cycle. The external bus cycle is all the set of signals being sent by the 68k to the external bus. The internal bus cycle is the state machine that drives this. During an address error, the internal bus cycle proceeds normally, as if the 68k were doing a perfectly valid bus access; however, the external bus cycle is effectively killed by the address error signal, as you describe. A bus error, on the other hand, stops the internal bus cycle cold as soon as it is detected.
Again, the actual implementation is not exactly as described by the patent. What the patent mentions is just a minor implementation detail. In one case the bus control logic receives the stop signal from other modules, on the other it generates it internally. Other than that, the processing is almost exactly the same. Bus error doesn't stop the bus cycle any more than on address error.

Edit: Will try to post some waveforms later
http://github.com/ijor/fx68k (68000 cycle accurate FPGA core)

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