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When doing DMA from the 68K address space to VRAM, what happens when the Z80 tries to read banked RAM memory during a long transfer?

I'd assume the Z80 is halted until DMA is over, but I think this would affect sample playback. Is there a priority system where the Z80 can always complete an access first and the DMA is temporarily paused, or is the Z80 access delayed until some defined interval? (I see /WAIT is connected to the Z80 in the schematics...)

Also unrelated to DMA, when the 68K has control of Z80 RAM via BUSREQ are there any wait states added when writing to Z80 RAM?

Charles MacDonald wrote:When doing DMA from the 68K address space to VRAM, what happens when the Z80 tries to read banked RAM memory during a long transfer?

I'd assume the Z80 is halted until DMA is over, but I think this would affect sample playback.

Your assumption is correct and it does indeed affect sample playback. That's one of the reasons why so many Genesis games have shitty sample quality.

Charles MacDonald wrote:Is there a priority system where the Z80 can always complete an access first and the DMA is temporarily paused, or is the Z80 access delayed until some defined interval? (I see /WAIT is connected to the Z80 in the schematics...)

There is no priority system. /WAIT is held until the 68K acknowledges the bus request which can only happen when the 68K has control of the bus. When the 68000 is running normally, there's typically a 3 Z80 cycle delay for acessing the banked area, but it can take 4 cycles if you get unlucky. It seems that when doing a word read/write, the second access will always incur an extra delay.

The only was to deal with sample playback during DMA is to buffer to Z80 RAM during portions of the display when there is no DMA going on.

Charles MacDonald wrote:Also unrelated to DMA, when the 68K has control of Z80 RAM via BUSREQ are there any wait states added when writing to Z80 RAM?

There's a one 68K cycle wait state when accessing the Z80's address space from the 68K.