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Does The DMA is using the external access slot to transfert data from/to vram?
What happen for example if there is a dma fill or dma copy and the 68k try to access vram?

mickagame wrote:What happen for example if there is a dma fill or dma copy and the 68k try to access vram?

Hell happens. Don't do it. That's why there's a DMA flag when reading $C00004.

mickagame wrote:Does The DMA is using the external access slot to transfert data from/to vram?

Yes

mickagame wrote:What happen for example if there is a dma fill or dma copy and the 68k try to access vram?

I haven't done any tests with DMA copy, but at least with DMA fill what happens is that the fill is temporarily interrupted for your new write and then the MSB of the word you just wrote is used for the rest of the fill. That's assuming you attempt to perform a write anyway. Not sure what happens if you attempt a read. I would assume that it would break the fill since CD would be changed to an invalid destination for writes.

Thanks for your answer.
Does the latency affect the dtack signal from vdp to 68K when perform a read or write operation?

mickagame wrote:Does the latency affect the dtack signal from vdp to 68K when perform a read or write operation?

Not quite sure I understand your question, but I'll try. For writes, !DTACK is held high until there is room in the FIFO to store the word being written. If the FIFO is not full, there is no delay. There is some latency involved in the FIFO, but only affects how early data written to the FIFO can get written to its destination. For reads, !DTACK is held high until the requested data is available. According to Nemesis, the VDP has a basic read prefetch mechanism so that it will perform the read after it's been setup in the control port as soon as there is an available external slot. I haven't tested it personally, but it makes a lot of sense and implementing it makes it easier to pass some of his tests.

I have a question about the control and data ports of the genesis.
Are these ports inside the vdp chips?
Often in emulator code these ports are outside the vdp code file.

The VDP control and data ports? Yes.

Emulators may handle them in a separate file since they're likely implementing them in the code handling memory accesses (which has no equivalent in real hardware, except maybe the bus itself), but emulators aren't necessarily modelling how real hardware works.

That confirm what i had in my mind ...
Thanks Sik !

Another question : what happen if the Z80 request the M68000?
The M68000 stop to execute opcode or it continues until it have to do a memory access (and at this moment it wait that the busreq line be back to 1)?

68K User manual suggests it is based on bus cycles rather than instruction cycles, I got the impression you can get the bus while an instruction is still halfway done.

The processor asserts BG as soon as possible. Normally, this process immediately follows
internal synchronization, except when the processor has made an internal decision to
execute the next bus cycle but has not yet asserted AS for that cycle. In this case, BG is
delayed until AS is asserted to indicate to external devices that a bus cycle is in progress

Thank you!

Yep, 68k should request the bus on every memory access, and release it when done, except for TAS.
Every memory access takes (a minimum of) 3 cpu cycles.