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Sega Megadrive/Genesis development
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Nemesis
Very interested
Joined: 07 Nov 2007
Posts: 456
Location: Sydney, Australia
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 Posted: Wed Apr 25, 2012 3:26 am Post subject: Sega TeraDrive motherboard pics |
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Hey, I've had a couple of TeraDrive systems sitting in storage for years now. A request from someone at AssemblerGames has seen me finally get them out and take some decent internal photos of the system:
http://nemesis.hacking-cult.org/MegaDrive/TeraDrive/Pictures
Here's what I wrote there:
"Most of the chips seem the same as the normal Mega Drive. The FM chipset in this case is a discrete YM3438, which we know is effectively the same as the YM2612. Apart from that, you've got your standard 315-5313, 315-5364, and 315-5309, same as an early model 1 Mega Drive. Probably the two most interesting chips on the board are U18 and U20. U18 has its board label partially covered by the green wires in those pictures, but it's labeled as "BUS SW". U20 is labeled as "DISP SW", and the writing on the chip didn't really turn out in the photos, but its markings are as follows:
NEC JAPAN
(C) IBM
9050KP004
79F2662
These two chips probably handle all communication between the two systems. I haven't traced any connections, but I think it's quite likely that the PC hardware is able to halt the M68000, and read/write into the Mega Drive RAM at the very least."
Figured some of you guys might be interested. One thing I haven't posted there which I find very interesting is that the TeraDrive seems to have 128Kb of VRAM for the VDP, IE, VRAM can run from 0x00000-0x1FFFF, not just 0x0000-0xFFFF. This is something I only became recently aware that the VDP supported, in some soon to be released documentation that hasn't been publically posted yet, it describes a Mega Drive development reference system, which has a lot of additional hardware mapped in to assist development. One of the things it provides is a 128Kb VRAM mode, which is apparently enabled by setting bit 8 of VDP register 2. I'm going to have to run some hardware tests on the TeraDrive and see if I can confirm this. |
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ElBarto
Very interested
Joined: 13 Dec 2006
Posts: 151
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TmEE co.(TM)
Very interested
Joined: 05 Dec 2006
Posts: 1946
Location: Estonia, Mahtra village
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| Posted: Wed Apr 25, 2012 9:35 am Post subject: |
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When me and Jorge Nuno were trying to decipher some lousy scan Amstrad Mega PC scans we also found a pin that's name suggested that VDP could use twice as much VRAM (on MD2 ASIC).
The guy is not wanting to scan that page in higher quality unfortunately.
Awesome photos BTW 
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Nemesis
Very interested
Joined: 07 Nov 2007
Posts: 456
Location: Sydney, Australia
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| Posted: Wed Apr 25, 2012 11:40 pm Post subject: |
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| TmEE co.(TM) wrote: | When me and Jorge Nuno were trying to decipher some lousy scan Amstrad Mega PC scans we also found a pin that's name suggested that VDP could use twice as much VRAM (on MD2 ASIC).
The guy is not wanting to scan that page in higher quality unfortunately. |
Is that this manual?
http://www.fvempel.nl/amstradcg/metia/mega.pdf
I don't know how you managed to make out anything from those scans, they're so poor. Are there other manuals floating around?
| ElBarto wrote: | | Can you check if any of the undocumented pins are connected to something (http://wiki.megadrive.org/index.php?title=315-5313)? maybe one of them is used to switch between two 64Kb banks. |
I don't have the board on-hand to check right now, but looking at the pictures I took, it appears that ALL of the undocumented pins are connected. I see traces running to pins 9, 14, 18, 19, 20, 21, 23, 24, and 25. I don't see a trace running to pin 22 on the top of the board, but it almost certainly runs back under the chip and through to the other side of the board. The underside board photo shows a line running out at the correct position to be that line.
I think I can shed some light on a few things here. I know from my work on the VRAM access timing that the VDP performs all reads from VRAM using a serial read mode. This read mode requires 7 full clock cycles to perform each read, with the first 3 clock cycles used for setup, and the latter 4 clock cycles used for data transfer, one for each bit of data (times 2 chips, so 8 bits of data as far as the VDP is concerned). This isn't fast enough to perform all the necessary reads for rendering, but read cycles can overlap by 3 clock cycles, where the setup for the next read is performed on clock cycles 5, 6 and 7 of the previous read, and the next read data starts being transferred on the very next clock cycle after the last read data has been fully sent.
The issue is, I don't think this kind of overlapped read model works if you have two independent banks of VRAM trying to share the same address lines. I'll have to check the datasheets, but I'm sure there'll be a problem that would prevent it from working, IE, some case where each VRAM bank requires the address lines to be valid, but asserting a different value. The VDP cannot strap all 4 of the 4-bit VRAM chips in parallel, it needs to have two separate banks to address that memory. With two separate banks of memory, the VRAM would need two separate sets of address lines for each bank, otherwise, it cannot correctly setup the second bank to start preparing for a read required from that bank until the first bank has completely finished transferring all the data bits for the current read. The data lines can be shared, since the data transfer itself never overlaps, but the address lines, and of course some of the control lines, need to be duplicated.
On that VDP pinout, pins 18-25 are, I would say, almost certainly the address lines for the second VRAM bank (IE, like 31-38 are for the first bank). Pin 9 is probably "SE1", IE, connected to the SOE lines on the second VRAM bank. Pin 14 is probably "WE1", IE, connected to the WE lines on the second VRAM bank. I'll have to trace the pins to confirm, but it seems highly likely. |
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Huge
Very interested
Joined: 13 Dec 2008
Posts: 147
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| Posted: Wed Apr 25, 2012 11:52 pm Post subject: |
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Holy shit, now this is A manual. I wish we had the type of detailed docs released nowadays. |
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Nemesis
Very interested
Joined: 07 Nov 2007
Posts: 456
Location: Sydney, Australia
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| Posted: Wed Apr 25, 2012 11:55 pm Post subject: |
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| You and me both! Hardware used to come with full schematics almost as a matter of course, and of course, there used to be general service centers where people actually got things fixed. Nowadays you just go out and buy a new one... |
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TmEE co.(TM)
Very interested
Joined: 05 Dec 2006
Posts: 1946
Location: Estonia, Mahtra village
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| Posted: Thu Apr 26, 2012 7:57 am Post subject: |
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Yep, that's the manual. I would suggest more people send him a mail and kindly asking to provide better scan, particularly that one page, so the ASIC pins names get all mentioned. Or maybe he could just write them down. We pretty much know all what they are, just not those "mystery pins"
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Charles MacDonald
Very interested
Joined: 21 Apr 2007
Posts: 210
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| Posted: Fri Apr 27, 2012 12:34 am Post subject: |
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Since so much of the VDP is set up with a 64K limit on VRAM addressing, would this only work in some clumsy way like selecting which one of two banks is being used for display purposes at any time? (sort of like the MSX2 VRAM expansion)
You mention the VRAM serial port is used primarily for display stuff; what is the regular 4-bit port mostly used for?
Very cool to see how big the boards are -- will you make some schematics for the Teradrive? I was worried everything would be hidden in a few custom parts but it's all out in the open here. |
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ElBarto
Very interested
Joined: 13 Dec 2006
Posts: 151
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| Posted: Fri Apr 27, 2012 5:08 pm Post subject: |
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| Charles MacDonald wrote: | Since so much of the VDP is set up with a 64K limit on VRAM addressing, would this only work in some clumsy way like selecting which one of two banks is being used for display purposes at any time? (sort of like the MSX2 VRAM expansion)
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Unused bit of table registers can be used for A16. Same for the address set, there is two bits left.
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Chilly Willy
Very interested
Joined: 17 Aug 2007
Posts: 1955
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| Posted: Fri Apr 27, 2012 6:29 pm Post subject: |
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| ElBarto wrote: | | Charles MacDonald wrote: | Since so much of the VDP is set up with a 64K limit on VRAM addressing, would this only work in some clumsy way like selecting which one of two banks is being used for display purposes at any time? (sort of like the MSX2 VRAM expansion)
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Unused bit of table registers can be used for A16. Same for the address set, there is two bits left. |
But pattern names are completely out of bits, meaning NONE of the extra memory can be used by what is most useful - patterns. The only way around that would be to add bits in the VDP registers to do something like shift ALL patterns for one layer or the other or the sprites completely to the other block, which is wasteful. |
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ElBarto
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Joined: 13 Dec 2006
Posts: 151
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| Posted: Sat Apr 28, 2012 12:40 pm Post subject: |
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Ah yes true, it was out of my mind ...
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Xavier
Interested
Joined: 30 Sep 2009
Posts: 16
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| Posted: Sat Apr 28, 2012 3:07 pm Post subject: |
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Do you have any of the floppy discs that these came with or manuals?
I just got one myself. I put dos 6.22 and windows 3.1 on it.
Id like to figure out a storage drive option. The hardrive ide cable is 44 pins I believe, a standardard ones 40.
I think itd be cool to get a sega cd attached to it. On youtube lingjr has one. Looks like a version 2 bios sega cd. Hes claims its a proto made just for the Teradrive.
The teradrives expansion is 30 pins or roughly the same as the cartridge slot, a Genesis ones in 28 off the top of my head.
Im also tring to figure out what would be the coolest thing to put in that isa slot. |
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Xavier
Interested
Joined: 30 Sep 2009
Posts: 16
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| Posted: Sat Apr 28, 2012 3:12 pm Post subject: |
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Double post.
Are there any other empty connectors? Theres a 10 pin one one the isa board called cn4 |
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Nemesis
Very interested
Joined: 07 Nov 2007
Posts: 456
Location: Sydney, Australia
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| Posted: Sun Apr 29, 2012 12:57 pm Post subject: |
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CN4 is the only empty connector that I saw, not sure what it's for.
I do have a full set of manuals and software for the system, that's one of the things I'm interested in right now actually, preserving documentation and software for this system, and the Amstrad MegaPC. I've got all the install disks I have for the TeraDrive backed up, and I'm about to attempt to take full images of the hard drives soon. I have both the system manuals, but I haven't scanned them in yet.
I will be releasing what I have into the public domain, but for the time being, I'm afraid I want to sit on the documentation and software I currently have. Unfortunately, very few people are forthcoming with releasing or sharing this kind of stuff, and I currently need some of this stuff as "barganing chips" to get other people to share what they have with me. It's not something I particularly like doing, but I think it's the best thing for the long-term goal right now of preserving this information, and making it available to everyone. |
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Huge
Very interested
Joined: 13 Dec 2008
Posts: 147
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| Posted: Sun Apr 29, 2012 1:00 pm Post subject: |
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| Just make sure you have proper backups of the thing. |
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