Posted: Sun Dec 07, 2014 12:27 am
@Chilly Willy: Interesting. What's the trick you're talking about?
@Mask of Destiny: yeah, one of the many fixes I'm gonna do. Might be tricky as no emulator exhibits this behaviour (but I got a modded MD2 that does)
@bastien: nice to hear, thanks
Regarding the z80 access timings, tests on a real MD revealed that what Mask of Destiny wrote seems to be correct. I played a low frequency sample so I could easily see missed writes in my audio editor after filtering the low frequency wave out.
68k delay / z80 T cycles / result
8 / <= 4 / lots of misses
12 / <= 4 / no misses at all
12 / <= 5 / a few misses (2 per second)
12 / <= 6 / lots of misses (50 per second)
Here's the transfer code with 12 cycles of delay:
Testing also revealed a bug in Exodus, it requires at least 18 cycles of delay for <= 4T, or else it will glitch. Or replacing the (a1) in the first line with $A11100 which also makes the bug go away in exodus (and my code slower). That's pretty odd, since I usually assume that the write cycle always happens last in an instruction, and as expected hardware testing shows that doing this replacement has no effect on real hardware regarding the glitches.
[Edit: more research on exodus bug to confirm that it's just an exodus bug and not a behaviour that occurs on real hardware too]
@Mask of Destiny: yeah, one of the many fixes I'm gonna do. Might be tricky as no emulator exhibits this behaviour (but I got a modded MD2 that does)
@bastien: nice to hear, thanks
Regarding the z80 access timings, tests on a real MD revealed that what Mask of Destiny wrote seems to be correct. I played a low frequency sample so I could easily see missed writes in my audio editor after filtering the low frequency wave out.
68k delay / z80 T cycles / result
8 / <= 4 / lots of misses
12 / <= 4 / no misses at all
12 / <= 5 / a few misses (2 per second)
12 / <= 6 / lots of misses (50 per second)
Here's the transfer code with 12 cycles of delay:
Code: Select all
move.w #$100, (a1) ; Request Z80 bus
swap d6 ; some delay
move.l d7, (a4)+ ; Write 2 samples
move.w d6, (a1) ; Release Z80 bus
[Edit: more research on exodus bug to confirm that it's just an exodus bug and not a behaviour that occurs on real hardware too]