Instruction timing test (68000)

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Ti_
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Instruction timing test (68000)

Post by Ti_ » Sun Jun 26, 2022 7:09 pm

Instuctions speed test (cycles count for instuction). Not sensitive to CPU speed.

Only several instuction done, but more can be easily added.

There's 3 rom version: one for emulators, one for hardware sega , and one for sega-cd in mode1.

1) Hardware test has timing values that matches hardware. Some long-time instruction a bit differs because of ram refresh (mul, div).
2) With sega-cd attached test executed on com-regs area, so the values here are accurate, not affected by refresher.
3) For emulator test is executed from rom, but has accurate values, as in sega-cd test.
Last edited by Ti_ on Thu Aug 04, 2022 7:33 pm, edited 1 time in total.

Ti_
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Re: Instruction timing test (68000), wip.

Post by Ti_ » Wed Jul 06, 2022 8:54 pm

Update - added about 400 instructions variations.
added pass/fail/total counter.

Now only 2 version of rom - for sega md/emulators, and for sega md with sega-cd.

When running on hardware, if instruction test was affected by refresh delay, now it shows in yellow color, and corrected value (no more 'odd' cycles). [For MD this happens only with mul / div / and specific long shifts, for sega-cd with some instructions that access to rom].
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Ti_
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Re: Instruction timing test (68000), wip.

Post by Ti_ » Sun Jul 17, 2022 8:16 pm

+ added a bit more instructions.
+ added exceptions instructions.
+ added variation of move.l on vram read/write (duplicates are some unrolled versions).

(some of them not available in sega-cd test version).
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Stef
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Re: Instruction timing test (68000), wip.

Post by Stef » Tue Jul 19, 2022 9:55 am

Very interesting but i'm not sure to understand the VRAM/VSRAM cycles number.
85 cycles is for VRAM read operation during display ON i guess and continuous operation ? what represent the first 19 cycles ? single VRAM read operation ? I'm also very surprised by the 11 cycles obtained on long VRAM write operation, should be 12 cycles there.

Ti_
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Re: Instruction timing test (68000), wip.

Post by Ti_ » Tue Jul 19, 2022 3:14 pm

Both sequences are repeated reading with display being off (DISP OFF), but second is more unrolled loop.

As for about '11' cycles of port. Test 'don't know' about dram 'refreshes' and cpu frequency.
All instructions timing calcuted by relative to others (to add.l d2,d0 and bra.s). Because all instructions executed from rom and do read/write only to/from rom, including stack-related instruction (sp is set on rom too), they all are affected almost same. Except long-cycles instructions: mul,div and some shifts, but not movem.l . Because of that test shows correct values for all. For mul,div and some shifts it's also correct but on hardware they became relatively faster and will be auto-corrected to +1 or +2 (and shown in yellow color).

But when doing writing on port, or on other non-rom address (as example $A12020), it's becomes relatively faster, because this areas not affected by refresh. This gives results in '11' cycles.
And if doing writing to ram ($FF0000), this will be slower , because ram has more refreshes delays, especcially when combined accesses (execute from rom + r/w from to ram). This will gives results in '13' cycles (I will add this variant with a new update).

So, in this cases, test shows not cycles count, but effective speed.
Stef wrote:
Tue Jul 19, 2022 9:55 am
Very interesting but i'm not sure to understand the VRAM/VSRAM cycles number.
I checked, and from emulators only exodus emulates this vram read slowdown approximately, but has many errors in others (including that it can divide by zero :lol: ).

Ti_
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Re: Instruction timing test (68000), wip.

Post by Ti_ » Tue Jul 19, 2022 8:28 pm

Here's an updated rom (only non-sega-cd version) with some extra modes - writing to ram, z80ram, r/w from vram/vsram with disp on, and with unknown commands.
Also - if value gets corrected, it's only yellowed, but not changed (extra modes sometimes gives a bit different values).

details on unknown commands:
UNK4 - #$00000030 (vsram read?)
UNK1 - #$40040020 (vram write?)
UNK2 - #$40040030 (vsram write?)

DISP = display on while test.
this tests as all others begins at v-int, and ends on next v-int (so it's shows averages speed including vblank time, and values here for NTSC console, will not match PAL).

Here's recording: video
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Ti_
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Re: Instruction timing test (68000), wip.

Post by Ti_ » Thu Aug 04, 2022 7:33 pm

Update:
+ added variations for bclr,bchg,bset on dx, these instructions timing differs if bits (0-15) or (16-31). All emulators ignores this.
+ values for access to vdp port with display being on now correct for PAL.
+ removed 'reset' instruction that causes some everdrives carts to reset.
+ added some more read/write ports areas.
+ unk4-read renamed to vram-read8bit.

Video record from PAL.
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test_inst_speed.7z
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